Jonathan Smith interview with Sean O'Kane ChipE...
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ARM TechCon 2011 commercia...
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Blogs

Koby's Kaos

The Future in 4D
blogger

The sleigh is ready, the presents packed, it’s the futures I’m worried about. Less wires, more batteries, the first...

JB's Circuit

More SI, Less EDA at DesignCon 2012
blogger

This year’s DesignCon show focused more on board-level signal intregity and testing issue than on chip design and...

Stan on Standards

Get Ready 'Cause Here It Comes: Accellera Systems Initiative Day @ DVCon
blogger

Lots of ink has been spilt (in a good cause) in reporting on the new Accellera Systems Initiative organization.  However...

Collaborative Advantage

Measuring Performance In Standards Development
blogger

Developing industry standards can be tough business. Getting them successfully, broadly adopted can be even harder. To...

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A Universal Capability to Assert OCP Compliance
The OCP-IP Functional Verification Working Group recently released to members a set of English language compliance checks that for... By Jeroen Vliegen – Chairman OCP-IP Functional Verification Working Group
Native SystemC Checkers Verify OCP-IP Specification Compliance
JEDA is developing verifcation automation tools for SystemC. One of our frst products includes a set of native SystemC assertions ... By Stephen R. Pollock, VP, Marketing and Sales, JEDA Technologies
OCP-IP Key to Design Reuse and Ease of Integration
capabilities. Eighteen month cycles have given way to 12 month and even 6 month cycles. To make matters worse, costs can drop dram... By Chuck Schalm, Director of Sales and Marketing at Jetstream Media Technologies
Sonics SMART Interconnects Meet the Challenges of Convergence SoC Design
The synergistic mix of multimedia and communications with Moore’s law has led to interesting challenges for SoC designers. A... By Jeff Haight – Director of Technical Marketing Sonics Inc.
Verification Components and Open Protocols: A win-win scenario for the design of modern electronic systems
The interaction between sub-components is critical (digital but also analogue) and is the major bottleneck in modern electronic sy... By Riccardo Mariani – Chief Technology Offcer, Yogitech
OCP System Level Design Working Group
Over the last few years Transaction Level Modeling has established itself as a valuable strategy to solve system-level design prob... By Anssi Haverinen – Chairman, OCP-IP System Level Design Working Group.

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