First of three parts: Market splits between those who can afford to keep up with Moore’s Law and those who cannot; when does it make sense for EDA companies to invest in new tools?

Second of three parts: Who’s to blame and why; big systems vs. specific problems; the economics of solving complex problems.

Last of three parts: Making progress with dirty data, a dearth of systems design engineers and the promise of 3D stacking.

First of three parts: A look at how the value is shifting in the supply chain and what’s driving it.

Second of three parts: Economics and Moore’s Law, the rising cost of software, the value of integration and IP.

Last of three parts: Disaggregation, reaggregation, the emphasis on low power and the rising value of IP and integration.

High-level synthesis raises the abstraction level, but it doesn’t eliminate the need for synthesizing at the RTL level; still no all-in-one solution.

Second of three parts: The accuracy of high-level synthesis, why it’s becoming more important and what are the limitations.

Last of three parts: Synthesis’ Holy Grail, the changing role of engineers and transaction-level modeling.

First of three parts: What makes one standard work while another one fails? Who has the advantage with new standards?

Have the cost of creating tools and the complexity of the problems become so great that the barrier for entry is higher? We asked the question and got some surprising answers.

System Level Design talks with Tom Quan of TSMC, John Koeter of Synopsys, Kalar Rajendiran of eSilicon and Phil Yastrow of Avago about where the value has shifted in the semiconductor design chain and why.

Where the next bottlenecks will be in high-performance computing and how to solve them.

Prasad Subramaniam, vice president of design technology at eSilicon, talks with System-Level Design Editor Ed Sperling about the challenges at future process nodes.

One-on-one: Synopsys CEO Aart de Geus looks at what’s changing in design and what’s driving those changes.

Multilayer non-volatile memory technology would boost capacity to 1 terabyte using standard processes and materials.

Freescale CTO Lisa Su talks about developing chips at 45nm, the increasing role of software and what’s missing from the tools flow.

This is the kind of equipment you wish you could play with.

More designs by fewer companies puts renewed value in the EDA world, according to Ray Bingham, managing director of General Atlantic, a private equity firm.…

Betting the future on a problem that has never been solved doesn’t bode well for continued sales of desktop and mobile computers.