System Bits: June 18
Graphene’s strength; controlling magnetism.
"What's the problem?" - ed

Deep Insights for Chip Architects and Engineers
Graphene’s strength; controlling magnetism.
Synopsys rolls out memory compiler; Silab rolls out PHY using Mentor tools; Cadence wraps buy of Evatronix; Dassault inks deal with Pininfarina; HPC market up.
DAC connections, George Clooney, compilers, blackmail photos, MIPI, Hawaii, platforms.
Complexity is causing huge increases in the number of unknowns in a design, from architectural modeling all the way through to manufacturing.
Functional models find their niches as the need to abstract certain parts of more complex designs becomes essential.
What does it really mean for engineers, especially in the high tech semiconductor industry, to design for experiences?
Both “subsystem” and “reuse” have definitions that are changing, making it a necessity to understand the context and the software requirements for each.
After struggling to find a foothold, a number of technological and business advancements are pushing formal into the mainstream.
Last of three parts: Who’s responsible when something goes wrong; security issues; local vs. cloud; re-usability of IP; what will speed up or slow down adoption.
Second of three parts: How chipmakers will differentiate; time-to-market issues; changes to the ecosystem; consumer concerns; standards; security.
Semiconductor, EDA, and IP companies must look beyond hardware and software to include factory manufacturing and supply-chain issues in their “systems” view.
Bridges are being built between the data center and mobile devices, opening new opportunities for EDA and IP—with some caveats.
A number of tools are now required to provide sufficient coverage, and design teams are rethinking what to use and when to use it.
FPGA-based prototyping is now indispensible for SoC and ASIC development.
Many semiconductor companies are considering skipping the 20nm node or staying longer at 28nm. What does this mean for semiconductor design?
First of three parts: What it is; what’s needed to make it work; why Moore’s Law doesn’t always apply; how it will be built; when it will ramp up; and who’s going to benefit and reap the profits.
Second of three parts: How chipmakers will differentiate; time-to-market issues; changes to the ecosystem; consumer concerns; standards; security.
Last of three parts: Who’s responsible when something goes wrong; security issues; local vs. cloud; re-usability of IP; what will speed up or slow down adoption.
First of three parts: What’s changed; the pros and cons of UVM; the evolving nature of complexity; three paths for verification; partitioning the verification; limits of formal, FPGA prototyping; relatively vs. absolutely correct.
Second of three parts: Different applications for tools; who’s doing the verification; automated assertions; the role of UVM; EDA opportunities and challenges; how things are really done.
Last of three parts: Verifying IP and software; using margin as a buffer; ‘happy gates’; deadly bugs; too many models; improving verification through better design.
First of three parts: IP qualification and verification; hierarchy of verification tasks; application-specific verification; re-using testbenches; knowledge transfer across the design flow; improving communication between hardware and software teams.
Second of three parts: Trust IP, but still verify it; what can go wrong; the danger of bugs in even non-critical IP; abstractions and use cases.
Last of three parts: Design variables for different markets; what’s good enough; uncertainty vs. innovation; big vs. small IP suppliers; future challenges with stacked die.
First of three parts: The need for speed and more complete tools; free tools vs. ASIC-level capabilities; timing closure problems; ASIC prototype vs. FPGA as the final product.
Why Cadence is buying IP companies and what the future of IP will bring.
What progress has been made in stacked die, when it will become mainstream and which markets will use it first.
What’s changing in verification as complexity continues to increase.
Complexity in designs, more features and smaller geometries are making it much harder to verify that a chip will work as planned.
One way to get more performance out of a design is to re-think what’s actually needed for a particular application. Not all applications require the same level of accuracy.
What will be necessary to get to 1 billion gates and what problems design teams will encounter along with way.
Cadence’s CEO talks about what’s changing in design, in Cadence, and across the global IC market.
A candid conversation with Open-Silicon’s CEO about the pain points in design, the challenges in derivative chips, and what’s missing from current tools flows.
Changes in the ecosystem and new requirements of SoCs are forcing companies to rethink coherency.
The push toward better performance in mobile devices is changing needs in SoCs designs.