Top Stories

SOI Goes Mainstream

Cheaper packaging, lower power consumption and limits on multicore software programming make a once exotic technology more viable.

Exclusive Research: Industry Hot And Cold Spots

Where the design activity is occurring and what the trends show.

Better Ways to Connect IP

IP-XACT is a major first step, but some experts say there are more challenges ahead.

Special Report: Semiconductor Road Map Survey

First look at the semiconductor industry’s new forecast; China grows as a global center of startup activity and R&D

Multicore Programming: The Next Frontier?

If no one can figure out how to scale applications, there may be serious ramifications to the entire electronics industry.

Devil in the Details: Trends in ASIC Prototyping

Changing market conditions and designer needs point to growth in software models and hardware prototypes.

OVM vs. VMM: What’s Next?

The biggest names in verification have figured out some possible solutions to incompatibility. After all, it’s in their best interest.

Reproducible Research – Studies in Open Source Hardware Design

But don’t expect miracles anytime soon…

Things You Never Knew About System Verilog

Despite popular myths, not everyone learned software programming in college.

Quality time?

What verification engineers say about the most time-consuming part of chip development.

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News Stories

Down, Down, Down

Analysis: What the economic downturn means for the chip industry.

SIA Outlook: Mixed

But semi industry chief says it’s time for action in Washington

Big Push for SOI

Teaming of IBM and ARM brings formerly exotic technology into mainstream, helping to create more energy-efficient designs.

Survival Skills For Engineers

The changing content at user groups may be the best indication yet that something is changing in the industry.

Return of Aluminum Interconnects

At older geometries chipmakers are measuring value versus what is needed by the application

Cadence Cleans House

Resignations” of five top executives viewed as significant and positive step by board; search for new CEO under way.

ARM Unfolds Road Map

Emphasis is on low power, small footprint, better performance and full suite of tools and support.

High costs, risk and complexity fuel new strategies

Get ready for some recycled buzzwords.

IP Grows Up

Industry shows signs of maturing with fewer players, tighter integration and even customization.

What Can Go Wrong?

Posted Sept. 24, 7 p.m.: IP and new processes make guesswork out of developing chips at the most advanced process nodes.

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Technology Features

Round Tables

Quality time?

What verification engineers say about the most time-consuming part of chip development.

Podcasts/Videos/Webcasts

Cognitive Radio

UC Berkeley’s Wireless Labs look at the challenges of utilizing the free, unused radio spectrum.

The Trouble With Serial Design

Complexity at the chip level is spilling over to board design.

Smarter Robots

At the Naval Postgraduate School in Monterey, Calif., the goal of these engineering students and professors is to create autonomous robot designs—ones that can be preprogrammed so that nothing can interfere with their design-in purpose

Verifying ASICs with FPGA Arrays

A look into the research underway at UC Berkeley’s Department of Electrical Engineering and Computer Science

Insider’s Guide to Complexity

ARM CEO Warren East talks about changes in system-level design.

Tires That Talk

A rare glimpse into system-level technology under development at the University of California’s Berkeley Wireless Research Center.

Digging into TLM 2.0

Mentor Graphics’ Jon McDonald talks about modeling strategies using the new standard.

Yet Another Type of IP

Yervant Zorian, chief scientist at Virage Logic, talks about infrastructure IP to ensure the health of a chip.

Runaway complexity, runaway costs

Why is it so expensive to develop new chips? We asked Virage Logic Executive VP Brani Buric.

DAC ‘08 Teaser Montage

http://www.youtube.com/watch?v=sXbpnmtuLWs&feature=related