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Top Stories

Blog Review – Monday, August 31, 2015

HPC for cancer analysis; body power: game on for animation; DDR challenges; aviation fascination; packaging checks; Arrow explains USB3.1; IDF meets IoT

Horizontal and Vertical Flow Integration for Design and Verification

System design and verification are a critical component for making products successful in an always-on and always-connected world.

Design and Verification Need a Closer Relationship

Concurrent development and verification of designs is more efficient and increases corporate organizational strength.

Blog Review – Tuesday, August 18, 2015

Where will the future of embedded software lead; Manufacturing success; DDR memory IP a personal view; Untangling the IoT protocols; The battle of virtual prototyping; Accellera SI ...

UVM goes to the IEEE

The Accellera Ssytems Initiative has released its UVM 1.2 standard to the IEEE for official standardization as IEEE18700.2. The Universal Verification Methodology (UVM) is providing ...

News Stories & Blog Reviews

Blog Review – Monday, August 31, 2015

HPC for cancer analysis; body power: game on for animation; DDR challenges; aviation fascination; packaging checks; Arrow explains USB3.1; IDF meets IoT

Blog Review – Tuesday, August 18, 2015

Where will the future of embedded software lead; Manufacturing success; DDR memory IP a personal view; Untangling the IoT protocols; The battle of virtual prototyping; Accellera SI ...

Blog Review – Monday, July 27 2015

IoT for ADAS; ESC 2015 focuses on security; untangling neural networks; what drives new tools; consolidation conundrum; IoT growth forecast; three ages of FPGA

Technology Features

Feature Articles

Horizontal and Vertical Flow Integration for Design and Verification

System design and verification are a critical component for making products successful in an always-on and always-connected world.

Design and Verification Need a Closer Relationship

Concurrent development and verification of designs is more efficient and increases corporate organizational strength.

System Design Enablement – Looking Beyond the Chip

System Design Enablement (SDE) will provide tools, design content, and services for the development of whole systems or end products.

Design Virtualization and Its Impact on SoC Design

At advanced technology nodes (40nm and below), the number of options that a system-on-chip (SoC) designer faces is exploding. Choosing the correct combination of these options can have ...

New ARM IP Tooling Suite Reduces Significantly SoC Integration Time

The new ARM suite addresses the most complex challenges associated with SoC configurability and assembly while reducing time to market.

Cadence Introduces Genus Synthesis Solution

Massively parallel architecture scales linearly beyond 10M instances while improving power, performance and area.

OneSpin Solutions Unveils 360LaunchPad a Unique, Third-Party Verification Solution

Advanced Formal Verification Technology Platform from OneSpin Used by Partner Companies in Range of New, Unique Verification Solutions.

Round Tables

Deeper Dive - A 3D-IC round table - part II

What’s needed for 3D-ICs to flourish? asks Caroline Hayes, senior editor. Experts from Mentor Graphics, Altera and Synopsys have some ideas for future progress.

Deeper Dive - 3D-IC Part 1 Fri. July 11 2014

As the industry transitions from 2.5D to 3D-ICs, Caroline Hayes, senior editor, asked experts from Mentor Graphics, Altera and Synopsys for their view on what system designers need ...

Deeper Dive - IoT Security

With new roles, IoT security will become even more important. Caroline Hayes, Senior Editor, asked Steve Kester, Shantnu Sharma (both AMD), Rich Rejmaniak (Mentor Graphics) and Rob ...

Deeper Dive - Is IP reuse good or bad?

Caroline Hayes, Senior Editor asked four industry experts, Carsten Elgert, Product Marketing Director, IPG (IP Group), Cadence, Tom Feist, Senior Marketing Director, Design Methodology ...

Internet of Things (IoT) and EDA

Things that seem simple often turn out not to be. Implementing IoT will not be simple because as the implementation goes forward, new and more complex opportunities will present

Verification Management

As we approach the DVCon conference it is timely to look at how our industry approaches managing design verification. Much has been said about the tools, but I think

Deeper Dive – Dec. 05

By Caroline Hayes, Senior Editor The twists and turns of FinFET In an earlier Deeper Dive (Nov. 21) we looked at how TSMC’s 16nm FinFET reference design was encouraging harmony ...

Podcasts/Videos/Webcasts

Saygus V2 Android Smartphone

Saygus V² (V Squared), winner of the CES 2015 Innovation Award, has 320 GB of storage, ARM-based Qualcomm Snapdragon 801, 21 MP camera, dual-boot capable, 2.5GHz quad-core processor, ...

CES 2015: Expanding the Connected Experience

Power-efficient ARM technology is everywhere you are, expanding your connected life.

Interview with Pebble Watch founder

Getting the Pebble Watch to Market. A conversation with Eric Migicovsky, Pebble founder and CEO

ARM TechCon Videos: Interview with Ian Drew. Part 3: Futures.

Embedded editor Chris A. Ciufo chats with Ian Drew, CMO, ARM. In part 3 of 3 "Futures", the guys discuss: adding IoT "intelligence at the node"; the Sensinode acquisition for

ARM TechCon Videos: Interview with Ian Drew (Part 2: 'mbedding' the IoT)

Embedded editor Chris A. Ciufo chats with Ian Drew, CMO, ARM. In part 2, the guys discuss: ARM's mbed/mbed OS and Cortex-M7; the easy path to the IoT is made

ARM TechCon Videos: Interview with Ian Drew (Part 1: Servers)

Embedded editor Chris Ciufo chats with Ian Drew, CMO, ARM. ARM's move into 64-bit servers with HP's recent “Moonshot” announcement; how the IoT grows from the enterprise and handsets; ...

Why IP Providers Need the New 1149.1/JTAG

Intellitech's CEO CJ Clark explains why the latest JTAG update brings much needed capabilities to IP providers and IC developers alike.