FPGA-based prototyping is now indispensible for SoC and ASIC development.

Many semiconductor companies are considering skipping the 20nm node or staying longer at 28nm. What does this mean for semiconductor design?

First of three parts: What it is; what’s needed to make it work; why Moore’s Law doesn’t always apply; how it will be built; when it will ramp up; and who’s going to benefit and reap the profits.

Second of three parts: How chipmakers will differentiate; time-to-market issues; changes to the ecosystem; consumer concerns; standards; security.

First of three parts: What’s changed; the pros and cons of UVM; the evolving nature of complexity; three paths for verification; partitioning the verification; limits of formal, FPGA prototyping; relatively vs. absolutely correct.

Second of three parts: Different applications for tools; who’s doing the verification; automated assertions; the role of UVM; EDA opportunities and challenges; how things are really done.

Last of three parts: Verifying IP and software; using margin as a buffer; ‘happy gates’; deadly bugs; too many models; improving verification through better design.

First of three parts: IP qualification and verification; hierarchy of verification tasks; application-specific verification; re-using testbenches; knowledge transfer across the design flow; improving communication between hardware and software teams.

Second of three parts: Trust IP, but still verify it; what can go wrong; the danger of bugs in even non-critical IP; abstractions and use cases.

Last of three parts: Design variables for different markets; what’s good enough; uncertainty vs. innovation; big vs. small IP suppliers; future challenges with stacked die.

First of three parts: The need for speed and more complete tools; free tools vs. ASIC-level capabilities; timing closure problems; ASIC prototype vs. FPGA as the final product.

Second of three parts: FPGA stacked die; application-specific debug; ASIC tools for FPGAs; changing methodologies; multiple FPGA devices; software issues.

What’s changing in verification as complexity continues to increase.

Complexity in designs, more features and smaller geometries are making it much harder to verify that a chip will work as planned.

One way to get more performance out of a design is to re-think what’s actually needed for a particular application. Not all applications require the same level of accuracy.

What will be necessary to get to 1 billion gates and what problems design teams will encounter along with way.

Cadence’s CEO talks about what’s changing in design, in Cadence, and across the global IC market.

A candid conversation with Open-Silicon’s CEO about the pain points in design, the challenges in derivative chips, and what’s missing from current tools flows.

Changes in the ecosystem and new requirements of SoCs are forcing companies to rethink coherency.

The push toward better performance in mobile devices is changing needs in SoCs designs.

A look at where the problems are in co-design and how much progress we’ve made.

Complexity, time-to-market, Moore’s Law and stacked die are all converging on the market for system-level design tools; growth begins to ramp.