First of three parts: Exploding complexity; bridging the language and engineering cultural gap; what’s really driving this market; who needs it and who doesn’t.

Second of three parts: Disjointed design schedules; approximately timed modeling; the limits and benefits of RTL, emulation and FPGA prototypes; general-purpose vs. highly specific processors in SoCs.

Last of three parts: Cost of models; synchronization problems; growing sense of optimism about co-design; differences between hardware and software; who’s in charge, and who’s being blamed for power problems.

First of three parts: Stacked die; the impact of software and integration; the changing role of EDA; who will be left standing and what they will make.

Second of three parts: Changes in the supply chain; what happens to little companies; rethinking business models; disruptions caused by stacked die.

Last of three parts: FPGA co-processors; virtualization; designs at 14nm; risks and guarantees for IP and subsystems; the value proposition for stacking die.

First of three parts: What’s behind system-level tool adoption; Japan and Europe lead; complexity surpasses human capabilities; ESL sub-flows around TLM and HLS; the growing challenges of verification in context.

Second of three parts: Stacked die and power; design exploration; standard models and interfaces; the cost of developing models; creating an interoperable ecosystem.

Last of three parts: Addressing software and power earlier; changing economics in design and new competitors; new roles for FPGAs; impacts of stacked die; what standards are needed.

First of three parts: Hardware-software co-design; raising the level of abstraction; pathfinding; finding commonality between designs and increasing re-use; modeling languages.

A look at where the problems are in co-design and how much progress we’ve made.

Complexity, time-to-market, Moore’s Law and stacked die are all converging on the market for system-level design tools; growth begins to ramp.

What’s working and what isn’t at advanced nodes for stacked die configurations.

The move to both fully-depleted SOI and FinFETs may be inevitable over the next couple process nodes, regardless of which one comes first.

Sonics CEO Grant Pierce looks at what needs to change in SoC design, what’s driving those changes, and how all of this will be affected by 2.5D and 3D stacking.

What are the design challenges of the leading GPU company and how are they changing?

Bernard Murphy digs down into what’s changing in semiconductor design and how 3D stacking will affect it.

A look at the next big thing in semiconductors and technology and what it’s going to take to get there.

Open-Silicon’s CEO talks about priorities in business and technology, and how to bring them together.

eSilicon’s CEO sounds off on changes in the supply chain, the skills needed to design a chip at 28nm and the promise of stacked die.