Experts At The Table: Where The Money Is
Second of three parts: Economics and Moore’s Law, the rising cost of software, the value of integration and IP.
"This great news for the Virtual Prototyping community that is so excited to see high level design and verification..." - Steve Brown

Deep Insights for Chip Architects and Engineers
Second of three parts: Economics and Moore’s Law, the rising cost of software, the value of integration and IP.
Analysis: The number of shifts that will occur over the next couple process nodes is unprecedented in the history of semiconductor design.
Meeting market and cost constraints means designers must sometimes forgo physical implementations in favor of software and that manufacturers must use hardware prototypes for initial product runs.
EDA vendors diverge on approaches as complexity grows at advanced process nodes; what do customers think?
Number of unwanted effects continues to rise, and so does the complexity of the design and the difficulty in getting chips to tape-out.
All the noise has been about the picture, but when it comes to audio the message is finally getting clearer.
Market adoption hinges on development of multiple types of through-silicon vias, standards, cost and market readiness.
Sub-40nm parametric effects push foundries to make DFM a mandatory handoff check.
Sci-fi editor says technology must be imagined before it is created.
Why SaaS hasn’t caught on in the SoC tools world and whether that will change in the future.
Synopsys buys VaST; Actel’s CEO to retire; financial reports bode well across the industry.
Odd videos, different priorities, design flaws, yield issues, and the iPad.
One language, two verification methodologies, eight solar plants and lots of zeros in the right place.
Verification, software quality, fast cars and 3D TV.
Actel flying high; Synopsys digs into India; AMD’s future, Rambus inks deal with Samsung.
Pink Floyd epiphanies, war, peace, tales of verification—and scrum.
I/O help to the rescue; a war of the foundry titans; the fine line between reality and fiction at the bleeding edge of technology.
Bring on the paparazzi; following Charlton Heston’s footsteps; new forms of compromise
Reading between the lines of all the releases there are strong signals that the recovery is well under way.
Bean counters, smackdowns and the other side of verification.
First of three parts: A look at how the value is shifting in the supply chain and what’s driving it.
Second of three parts: Economics and Moore’s Law, the rising cost of software, the value of integration and IP.
High-level synthesis raises the abstraction level, but it doesn’t eliminate the need for synthesizing at the RTL level; still no all-in-one solution.
Second of three parts: The accuracy of high-level synthesis, why it’s becoming more important and what are the limitations.
Last of three parts: Synthesis’ Holy Grail, the changing role of engineers and transaction-level modeling.
First of three parts: What makes one standard work while another one fails? Who has the advantage with new standards?
Second of three parts: Models, standard languages and software’s role model—or lack of a role model.
Last of three parts: The accuracy of models, the adaptability of standards and what can go wrong.
First of three parts: Why even the largest companies are abandoning their internally developed tools and where the next standards will be.
Second of three parts: Why standards are important to companies, how they happen and why it takes so long.
System Level Design talks with Tom Quan of TSMC, John Koeter of Synopsys, Kalar Rajendiran of eSilicon and Phil Yastrow of Avago about where the value has shifted in the semiconductor design chain and why.
Where the next bottlenecks will be in high-performance computing and how to solve them.
Prasad Subramaniam, vice president of design technology at eSilicon, talks with System-Level Design Editor Ed Sperling about the challenges at future process nodes.
One-on-one: Synopsys CEO Aart de Geus looks at what’s changing in design and what’s driving those changes.
Multilayer non-volatile memory technology would boost capacity to 1 terabyte using standard processes and materials.
Freescale CTO Lisa Su talks about developing chips at 45nm, the increasing role of software and what’s missing from the tools flow.
This is the kind of equipment you wish you could play with.
More designs by fewer companies puts renewed value in the EDA world, according to Ray Bingham, managing director of General Atlantic, a private equity firm.…
Betting the future on a problem that has never been solved doesn’t bode well for continued sales of desktop and mobile computers.
Jim Hogan, long-time investor and VC, talks about what’s changing in system-level design and what it will take to be a survivor.