Memory Design Considerations When Migrating to DDR3 Interfaces from DDR2
Introduction
This white paper provides the reader with a detailed understanding of the key design considerations when migrating to a DDR3 system interface from a DDR2 interface and reviews the new DDR3 features, comparing and contrasting them to previous features available in the DDR2 specification. The biggest changes are the tightened timing requirements in the Physical Layer (PHY) portion of the memory interface. These changes are highlighted and illustrated with an example design of a high performance processor interface. The areas where backwards compatibility should be maintained are also illustrated with an example design, showing how simple changes can provide significant benefits in reuse and system flexibility.
A Comparison of DDR2 and DDR3 Memory Standards
The DDR2 memory standard is being upgraded with the advent of the DDR3 standard. The variety of memory devices available today provides the system architect with multiple options when selecting a memory. Before going into the detailed comparison of DDR2 and DDR3, let’s review the key features of a typical DDR2 memory subsystem and the associated memory controller. This will serve as a baseline for the detailed comparison.
DDR2 Description
A typical DDR2 memory subsystem uses a DIMM (Dual In-line Memory Module) to house multiple DDR2 memory devices. A typical DDR2 DIMM architecture is illustrated in Figure 1 below. The control and address signals come onto the DIMM and are routed to the memory devices in a T-branch topology. This architecture balances the delay to each memory device, but introduces additional skew due to the multiple stubs and the different stub lengths for each signal.
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Figure 1. DDR2 Dual In-line Memory Module Architecture
A DDR2 memory controller is located on the chip driving the DIMM module. A typical DDR2 memory controller is show in the block diagram in Figure 2. The PHY (Physical Layer) sub-system is responsible for the physical interface between the DDR DRAM (Double Data Rate Dynamic Random Access Memory) and the rest of the system. Timing is controlled precisely to insure data is captured or presented in just the right relationship with the DRAM clocking signals. Data read from the DRAM is optionally corrected by the ECC (Error Checking and Correcting) block and provided to the pending write FIFO (First In First Out). If ECC is being used, the ECC check bits are computed prior to the write to memory by another optional ECC block in the write path.
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Figure 2. DDR2 Functional Block Diagram
The scheduler (made up of the NT – Next Transaction, BSM – Bank State Machine, OS – Operation Selection, and GS – General State machine blocks in the middle right of Figure 2) prioritizes the current list of commands determining which command is the most urgent and then issues that command to the DRAM. Data is read or written to the memory based on the scheduler’s computation of access priority. The scheduler constantly works towards the goal of maximizing overall system efficiency and bandwidth while issuing all high priority commands as quickly as possible.
Commands are optionally pipelined and added to the pending FIFO. If the command is most urgent (direct read) it bypasses the pending FIFO and is issued directly to the memory. Regular priority accesses make their way through the pending read FIFO or the read token FIFO for command completion.
DDR3 Description
The main thrust of the DDR3 memory standard is to increase memory bandwidth while making it relatively easy for the designer to take advantage of this bandwidth increase. Innovations in the PHY portion of the DDR3 interface support this increase in bandwidth. The PHY innovations include Read and Write Leveling capabilities which allow for independent timing adjustments for the Read and Write paths. Innovations outside the PHY also help improve overall performance and reliability of DDR3 designs. These changes include a Reset Pin, to insure the proper initialization of the memory devices, an increase in the pre-fetch size to 8 bits from the 4 bits used previously in DDR2 and a ZQ calibration feature to simplify the calibration adjustment process. Each of these innovations will be explained in more detail in the following sections. We will start with a description of the DDR3 leveling features and then move on to the other DDR3 features.
DDR3 Leveling Features
The DDR3 specification can support a fly-by architecture either on a memory module or on a board. In this architecture, illustrated in Figure 3 below, the signals from the memory controller are connected in series to each memory component — in effect flying by each component instead of stopping there as in the DDR2 implementation shown in Figure 1. In a DDR3 memory module, the signals from the DDR3 PHY come into the middle of the module and connect to each memory chip sequentially. This reduces the number of stubs and the stub lengths. Termination is placed just at the end of the signal. This improves the signal characteristics over the traditional DDR2 topology.
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Figure 3. Fly-by Topology for DDR3 Un-buffered DIMM
The drawback to this approach is that the delay from the PHY output signals to each memory is slightly different, depending on where the memory chip is in the sequence. This delay difference needs to be compensated for by the DDR3 PHY, therefore it uses the new leveling feature required by the DDR3 specification. There is a different technique for both Write and Read Leveling.
Write Leveling
During Write Leveling, the memory controller needs to compensate for the additional flight time skew (difference in the signal delay to each memory device) introduced by the fly-by topology with respect to strobe and clock. In particular, the tDQSS, tDSS and tDSH timing requirements (those related to skew between the data strobe and clock) would be very difficult to meet. These timing parameters can be met by using a programmable delay element on DQS with fine enough granularity so the proper delay can be inserted to compensate for the additional skew delay. Figure 4 shows the needed timing relationship.
The source CK and DQS signals are delayed in getting to the destination, as illustrated by arrow #1 and arrow #2 respectively. This delay can be different for each memory component on the memory module and will be adjusted on a chip-by-chip basis and even on a byte basis if the chip has more than one byte of data. The diagram illustrates just one instance of a memory component. The memory controller repeatedly delays DQS, a step at a time, until a transition from a zero to a one is detected on the destination CK signal. This will realign DQS and CL so that the destination data on the DQ bus can be captured reliably. Because all this is done automatically by the controller, the board designer need not worry about the details of the implementation. The designer benefits from the additional margin created by the Write Leveling feature in the DDR3 memory controller.
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Figure 4. Timing Diagram for Write Leveling
Read Leveling
During Read Leveling, the memory controller adjusts for the delays introduced by the fly-by memory topology that impact the read cycle. This is done via the addition of a special Multi-Purpose Register (MPR) in the DDR3 memory device. The MPR can be loaded with predefined data values via a special command from the memory controller. These data values can be used for system timing calibration by the memory controller.
As shown in Figure 5, the MPR can be selected by setting a bit in another memory register (EMRS3, bit A2) to switch the source of data for memory read to come from the MPR, not the normal memory array. The MPR data is substituted for the DQ, DM DQS and /DQS pads on the memory device. This feature allows the memory controller to calibrate the timing of the read path to adjust for any additional delays introduced by the DDR3 fly-by architecture. Delays will be computed and inserted in the appropriate signals inside the controller to adjust for these additional read path requirements.
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Figure 5. Read Leveling Using MPR
Additional DDR3 Features
DDR3 has additional features to improve performance and reliability. These include a Reset Pin, an 8-bit pre-fetch, and ZQ calibration. A new Reset Pin is used to clear all state information in the DDR3 memory device without the need to individually reset each control register or power down the device. This saves time and power when bringing the device to a known state. The 8-bit pre-fetch is used in conjunction with burst lengths of 4 or 8. This improves performance for sequential accesses. The new ZQ calibration feature allows the memory device to take a longer time for calibration at start-up and a smaller time during periodic calibration activities. Table 1 below shows a feature-by-feature comparison of DDR, DDR2 and DDR3 memory devices.
| Â | DDR | DDR2 | DDR3 |
| Data Rate | 200-400Mbps | 400-800Mbps | 800-1600Mbps |
| Interface | SSTL_2 | SSTL_18 | SSTL_15 |
| Source Sync | Bi-directional DQS (Single ended default) | Bi-directional DQS (Single/Diff Option) | Bi-directional DQS (Differential default) |
| Burst Length | BL= 2, 4, 8 (2bit pre-fetch) | BL= 4, 8 (4bit pre-fetch) | BL= 4, 8 (8bit pre-fetch) |
| CL/tRCD/tRP | 15ns each | 15ns each | 12ns each |
| Reset | No | No | Yes |
| ODT | No | Yes | Yes |
| Driver Calibration | No | Off-Chip | On-Chip with ZQ pin |
| Leveling | No | No | Yes |
Table 1. DDR, DDR2 and DDR3 Feature Comparison
Planning For Migration — An Example Design
In order to explore how to prepare a DDR2 design for migration to a DDR3 design, it will help to establish an example system. Let’s assume that the system will require a DIMM interface for DDR2 and will need to use a similar type of memory module in the DDR3 implementation. Performance is increasingly important for many applications so the decision is to initially design the controller as a DDR2 design, but to allow future migration to DDR3. As much as possible, we want to make it easy to modify the board and the memory controller to migrate from the DDR2 implementation to a DDR3 implementation.
Board Level Issues
One of the biggest issues when thinking of migrating from DDR2 to DDR3 is that the DDR2 and DDR3 DIMMs have different pin-outs and sizes. This means that it will be very difficult, at the board level, to create a single DIMM receptacle and then be able to plug in either a DDR2 or DDR3 memory module. The best approach is to take into account the key board level differences between the two standards, and by planning ahead make it easier to implement changes to the board (modify the DIMM footprint and change some traces) for a DDR3 module. For example, it should be possible to plan for the inclusion of the DQS change and the Reset Pin ahead of time, in order to make it easier to add the DDR3 DIMM footprint and re-layout the board.
DQS
In DDR3, DQS is specified as differential while in DDR2 it can be single ended or optionally differential. Clearly, if the differential version is used in DDR2 it will make the transition to DDR3 easier. This may require additional pins in the memory controller, but if upward compatibility is important the extra pins will be worth it. The DDR2 implementation will also be more robust.
In DDR3, the DQS is sourced by each memory device in order to account for the additional delay from the fly-by topology. The number of DQS signals is therefore larger in the DDR3 implementation than in the DDR2 version. Again, if the additional pins are not a concern, it will help with the migration to DDR3 in implementing the additional DQS signals in the DDR2 implementation.
Reset Pin
The Reset Pin present in DDR3 is easy to add to DDR2. Although the pin will not do anything in the DDR2 implementation, although including it will insure that the pin is available when it is time to migrate to DDR3.
Memory Controller Issues
Other aspects of the DDR2 to DDR3 migration will require some impact to the memory controller. If the DDR2 memory controller is designed with some of these issues in mind, it can simplify the process considerably. Some of the most important issues are the Output Drivers, DLLs (Delay Locked Loop – the key building block for adjusting timing for critical periodic signals) for Write Launch, and Read Leveling.
Output Drivers
The DDR2 standard calls for 1.8V SSTL I/Os. DDR3 calls for 1.5V SSTL I/Os. It may be difficult to find an I/O buffer that can support both standards. It might require a programmable I/O, similar to those found on FPGAs (Field Programmable Gate Arrays), to support both standards. A change in I/O buffers would require a spin of the chip driving the DDR3 memory, but perhaps a metal mask option could be used to make this change less expensive.
DLLs for Write Launch
Typical DDR2 memory controllers can get away with one DLL for several data outputs. In DDR3, due to the fly-by topology, it will be more usual to see a DDL for every 8-bits or so. This would require a larger number of DLLs to be included in the DDR2 design in order to provide the resources required for the DDR3 migration. A digital DLL implementation can be very compact in die size and can minimize the overhead associated with the DDR3 requirement.
Read Leveling
Typical DDR2 memory controllers use an extra pair of I/O pins to calibrate the controller read timing. These pins are used to help adjust the incoming data with respect to the strobe. Other controllers use a training sequence by writing and reading data from memory and adjusting the strobe to optimize the data capture point. In DDR3, the Read Leveling feature is used to do this and requires no additional pins. If the memory controller can be designed to include the Read Leveling feature, even if not used in DDR2, it would help significantly with DDR3 migration.
SUMMARY
DDR3 offers a substantial performance improvement over previous DDR2 memory systems. New DDR3 features, all transparently implemented in the memory controller, improve the signal integrity characteristics of DDR3 designs so that higher performance is achieved without an undue burden on the system designer. If proper consideration is given to any new DDR2 memory design, it can be a relatively easy upgrade to support DDR3 in the next generation design. This paper identified the key differences between DDR2 and DDR3 and illustrated some of the key issues that need to be addressed for easy migration to DDR3.
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