What Can Go Wrong?
By Ed Sperling
Sept. 24, 2008—Santa Clara, CA—Verifying intellectual property blocks at the bleeding edge of technology is as much guesswork as it is engineering, and the result is often a combination of bad yields, bad chips, and truly bad business choices.
Two panels at the GSA-IP conference here looked at the chip design business at the most advanced process nodes, both arriving at similar conclusions. Because IP has to be developed as early as possible for each node, and because process technology is not stable at first, the marriage starts out like two people who have never met. At best it doesn’t work optimally. At worst, it’s a disaster.
“If I have a brand new standard and IP, I will do the best I possibly can at every node,” said Kamalesh Ruparel, VP and general manager of ASIP Solutions at Virage Logic. “But it can’t be 100% validated. The only thing we can do is put a process in place for consistent improvement.”
Ming Hsu , VP of worldwide IP support at foundry UMC, called it a “chicken and egg problem. We know the process is not mature. It has a learning curve, and that takes time.”
Ruparel noted that large customers often get the benefit of lots of attention from the foundries and know which questions to ask. Midsize companies, meanwhile, typically don’t get fully validated IP. “It is a nightmare for them. You’ve got DFM, ever-changing parasitics and new SPICE models. The problem is that a lot of customers don’t know what to ask for. IP is moving so fast that what we see a lot of times is buzzwords.”
Even where digital IP can be verified, analog typically cannot. The list of things that can go wrong in a mixed signal SoC are endless. Robert Heaton, director of analog solutions architecture at MIPS Technologies, said there are no consistent methods for verifying mixed-signal chips. “It’s not universally formalized,” he said. “There are no tools.”
In addition, because IP is changing so quickly and chips are becoming so complicated, the checklists that companies use to make sure they’ve checked everything are quickly outdated, Heaton said.
Nevertheless, it often is the IP that is the problem in low yields and chips that don’t work. Wayne Dai, CEO at VeriSilicon, said his company has a 90 percent rate for first silicon. He said the other 10 percent is almost always due to IP problems.
Tags: DFM, IP, Mixed Signal, Verification