IP Grows Up
By Ed Sperling
The idea that IP blocks would be as interchangeable as Legos is proving impossible to implement. In its place, consolidation of IP vendors touting integrated suites of IP are becoming the rule rather than the exception.
This week, both ARM and Virage Logic began touting integrated packages of physical, memory and logic IP, along with tighter relationships with big foundries. Both deals are significant from an SoC perspective, because they point to a maturing market for IP, where complexity, increasing costs and fewer customers at the bleeding edge are shrinking the number of players.
This should sound very familiar to anyone who has watched the EDA industry over the past decade. Integrated flows replaced individual tools, and even in cases where the tools offered in those flows weren’t best of breed, the value of the integrated pieces proved at least, if not more, valuable to many designers than having the best point tools. And in the case of IP, consistency and guaranteed peformance is at least as important as innovation.
IP vendors won’t get off that easily, however. While IP does shorten the development process, each IP block has to be verified for every manufacturing process. That means dozens of iterations for every IP block, and at the most advanced nodes where processes are not well defined and tested, it still might not work right.
That puts the burden on the foundries and the IP developer to raise designs to a higher level of abstraction, something that becomes more difficult at every process node. The goal, according to Simon Segars, general manager of ARM’s Physical IP division, is to “abstract away the underlying horror.” ARM inked a deal with the Common Platform companies—IBM, Chartered Semiconductor and Samsung—to jointly tackle the integration and consistency challenge.
“There’s a lot more integration than you’d expect,” said Dean Freeman, an analyst at Gartner. “The advantage is that ARM is networked and integrated with everyone because of its cores—everything from cell phones to the Power architecture.”
Virage Logic cut a similar deal with IBM and Chartered, and a more extensive one with TSMC. The TSMC one is particularly interesting, because it involves what amounts to custom work for top customers—something that Virage has the right to refuse if it doesn’t think it can turn a profit on the deal.
“What we’re finding is that there is more and more investment in new and existing process nodes,” said Brani Buric, executive vice president of marketing at Virage Logic. “Everyone is trying to get the maximum out of 90nm so they’re going to 85nm and then to 80nm.”
He noted that TSMC wants IP available as early as possible for each half-node and every new process node. But more than anything, it more tightly integrates the front end of design with back-end manufacturing. Now the question is how much pain that eases for what goes on in between.
