By Ed Sperling & John Blyler

For all the concern about 45nm chip development—and there have been a number of design investigations at that process node since the beginning of the year—the vast majority of activity is still at 130nm.

This is an indication of just how costly it has become to stay on the Moore’s Law road map—and how many companies have stopped trying to keep up. It’s also an indication of just how much life is left in the older process nodes. Since the beginning of the year, there have been more than 13,000 design investigations—trying out new tools, architectures and processes. Roughly 12 percent of those were at 45nm, with 60 percent at either 90nm or 130nm.

This has multiple implications for the industry, and particularly the fabless development model. While companies such as Broadcom, Qualcomm, Nvidia and AMD continue to live on the bleeding edge of the fabless world, the vast majority of chip developers have adopted strategies that either hang back one or two nodes or skip nodes entirely. Because of the expense of developing new chips, the number of chips that need to be sold to generate a profit has been steadily rising.

Within the foundry business, however, there have been two very distinct models. While companies such as TSMC, UMC and the Common Platform triumvirate of IBM, Samsung and Chartered Semiconductor continue to lead the pack to the next process node, that leadership comes at a very high price. Others, such as China’s SMIC, Israel’s Tower and Malaysia’s Silterra continue to erode their profits several nodes back where volume is significantly higher.

Joanne Itow, managing director for manufacturing at Semico Research, said the number of wafers processed at the leading edge continues to grow. That’s a function of how much volume is necessary to break even at advanced nodes. But Itow said that also translates into more foundry business at the leading edge than there was five years ago. Within that scenario, there also is more competition.

At the same time, she said 130nm remains popular for a variety of reasons: “It can be run with or without copper, on 200mm or 300mm wafers, and there is still a lot of capacity at 130nm. So the price is very competitive and it is not surprising that companies will continue to utilize that technology for a long time. As the price to manufacture declines, we (consumers) benefit from the new electronic applications that emerge. New designs at 130nm are taking advantage of the technology at very good price points.” Apple’s iPhone is only one example of new consumer designs that use 130nm technology.

For capital equipment makers, this isn’t particularly good news. Fewer foundries at the leading edge mean fewer sales. The abandonment of the 200mm fab equipment by memory makers has left a lot of used equipment for sale, said Itow. Big foundries have depreciated their equipment and remain competitive on pricing against second-tier foundries, but the overall effect on capital equipment sales is significant.

This also has implications for the EDA industry, although low-power design starts and a focus on business objectives versus raw performance could pry open a replacement market as well as drive new markets. As expected, the vast majority of design investigations occurred at 100MHz and 50MHz. Low power has become not only a mandate but an opportunity for chip developers, and many companies have begun developing multicore chips that run at lower clock speeds—or are using multiple chips at lower clock speeds.

Systems on chip, in particular, seem to be gaining momentum. Of all design activity, nearly 40 percent of those questioned used at least one block of non-memory IP, and some used more than 30 blocks. That figure is a strong indication of time-to-market pressures and the maturity of the IP industry, as well as an indication of how companies are crafting their chips.

Interestingly, the bulk of the lower clock speeds are being developed at older process nodes, not at the bleeding edge. Speed is still important, but as a selling point power is at least as important, if not more important. In fact, since January there have been only 23 investigations into chips running at clock speeds greater than 3GHz.

By region, most of the design activity occurred in North America. Asia, including Japan, saw only about one-fourth as much activity as North America in 2008. Despite all the startups in China and the preponderance of manufacturing there, the bulk of the design activity remains in North America. Asia was tied with Europe.

Tags: Architectural, ASIC, EDA, systems engineering, systems engineering management

This entry was posted on Thursday, November 20th, 2008 at 6:00 am and is filed under Top Stories. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.