Comments on: Experts At The Table: The Mixed Signal Challenge http://chipdesignmag.com/sld/blog/2009/01/02/experts-at-the-table-the-mixed-signal-challenge/ Deep Insights for Chip Architects and Engineers Wed, 15 Jun 2011 14:29:30 +0000 hourly 1 http://wordpress.org/?v= By: Kevin Cameron http://chipdesignmag.com/sld/blog/2009/01/02/experts-at-the-table-the-mixed-signal-challenge/comment-page-1/#comment-6514 Kevin Cameron Sat, 11 Jul 2009 18:04:16 +0000 http://chipdesignmag.com/sld/?p=1292#comment-6514 It would help a lot if the people with the problems would actually turn up at the committees and drive the process. The Verilog-AMS language has been stuck at Accellera for a decade when it should have been rolled into the IEEE Verilog efforts, in which case we would have a SystemVerilog-AMS language by now. As it is, a unified AMS flow is probably still some years off. A top-down/bottom-up AMS design flow with IP reuse requires that things like back-annotation work correctly for behavioral descriptions, and as far as I can tell nobody is working on that problem for AMS. A related issue is how you handle power distribution/management, and that doesn't seem to be making a lot of progress either in the HDLs, so people are resorting to defining external standards (LPF etc.). This has also led to people trying to add AMS assertions to SystemVerilog, while there is still no support for analog design in SystemVerilog! So I would say "yes we can" automate mixed-signal design, but it's going to require a lot of work on the low level tools and standards first. It would help a lot if the people with the problems would actually turn up at the committees and drive the process. The Verilog-AMS language has been stuck at Accellera for a decade when it should have been rolled into the IEEE Verilog efforts, in which case we would have a SystemVerilog-AMS language by now. As it is, a unified AMS flow is probably still some years off.

A top-down/bottom-up AMS design flow with IP reuse requires that things like back-annotation work correctly for behavioral descriptions, and as far as I can tell nobody is working on that problem for AMS. A related issue is how you handle power distribution/management, and that doesn’t seem to be making a lot of progress either in the HDLs, so people are resorting to defining external standards (LPF etc.). This has also led to people trying to add AMS assertions to SystemVerilog, while there is still no support for analog design in SystemVerilog!

So I would say “yes we can” automate mixed-signal design, but it’s going to require a lot of work on the low level tools and standards first.

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