DFM Moves From Hype To Reality
By Ed Sperling
Santa Clara, Calif.—Feb. 5, 2009—Design for manufacturing was a great buzz phrase for the past five years, but at 45nm and beyond DFM is becoming a necessary approach. As a result, differences between system-level designers and foundries have escalated from hypothetical to tangible.
Joe Sawicki, vice president and general manager of Mentor Graphics’ Design-to-Silicon Division, said during a panel at DesignCon that DFM has moved from the hype phase to the “slope of enlightenment.” He added that at the 45nm and 32nm process nodes it will become a design diagnostic requirement.
That also means DFM needs to be developed and tested like any other suite of tools in chip design. Kimon Michaels, vice president and general manager for DFM at PDF Solutions, said much of the data that DFM tools now provide are “overly conservative.”
“There is a need to provide DFM data that is accurate and practical for both the foundry and fabless companies,” Michaels said. He noted that the quantity of the data has not been a problem. There is plenty of available, but not of the quality necessary to avoid respins and ensure manufacturability of designs.
To a large extent, this depends upon cooperation between the fabless companies and the foundries that manufacture their chips. That cooperation has improved over the past several years, but there is still hesitancy on both sides to cement a partnership.
On the side of the developers, Mark Radford, Cambridge Silicon Radio, said questions remain about the data. “The foundries provide DFM kits and SPICE models and EDA provides tools,” he said. “But does the data statistically capture what we want and the level of detail we need?”
The answer to that question becomes increasingly important at every new process node. “At 32nm and 28nm, variability will be the dominant new challenge,” Radford said. “There will need to be DFM checks on third-party IP. All parties must work much more closely together. Right now there is competition and suspicion. We need to find a collaborative EDA, fabless and foundry working model.”
All of this concern—by EDA companies, foundries and end users—signals a change in how companies are looking at DFM. Walter Ng, senior director of design solutions at Chartered Semiconductor, said that until now there has not been a lot of adoption of DFM by customers.
“The big question now is, ‘Do customers see the value of purchasing additional tools,’” he said. “Through 65nm, we have not seen much impact.”
Ng noted that DFM will be most needed where there is the least amount of silicon—at the leading edge of development—and where variation tends to be greater because there has been limited learning on a new process. He said that variability decreases as volume increases and processes can be refined, but there is a challenge for companies looking to utilize the most advanced process nodes.
Among the problems is the cool air thermal limitation of 100 watts per square centimeter, said Jamil Kawa, group director of Synopsys’ advanced technology group.
“Voltage is not scaling properly anymore,” Kawa said. “There is also an increase in short-channel effects. Silicon trench isolation will be difficult unless we move to SOI (silicon on insulator) or finFETs. In addition, planarization will become very critical.”
Tags: CSR, DFM, fabless, foundries, Mentor Graphics, PDF, Synopsys