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Architectural Design Companies Drop ESL Moniker

By John Blyler
More and more companies on the software or “soft” side of chip design are distancing themselves from the Electronic System Level (ESL) design terminology. Who can blame them? ESL has been so hyped that it’s come to mean the near-instantaneous generation of optimized RTL-based hardware from high-level software algorithms. Anyone involved in the rigorous exercise of performing architectural trade-off studies between chip power-performance-area constraints will tell you of the complexities involved with concept to hardware implementation of such designs.

It’s natural for companies to want to tailor their interpretation of the meaning of ESL to best showcase their best products. Take Virtutech, for example, which prefers the term “Virtualized Systems Development” (VSD) over ESL. VSD uses virtual target hardware for software and system development. This target hardware is microprocessor-based, predominantly PowerPC architectures.

The key to VSD development lies in fast simulation of system software at an architectural level. Using a Virtualized System Development approach provides a way to do “what if” exploration, before the cost of hardware is locked in, notes Michel Genard, VP of Marketing for Virtutech. “VSD provides a platform to take your existing software and try it on a different hardware environment, most often a multicore system.”

VSD provides software developers with a fast method to run their programs. Such an approach relies on system-level IP libraries of the processor architectures under investigation.

Another software-centric approach to ESL is CebaTech, which recently repositioned itself as a software-to-silicon IP cores company. “We are neither an ESL tool vendor nor a design-services company,” explained Ramana Jampala, CEO of CebaTech. “Our real competency is a compiler that can input untimed ANSI-C and output synthesizable RTL, ready for to be used by any EDA tool.”

Although CebaTech does not compete in the same markets as Virtutech, both companies emphasize the importance of high-level architectural explorations where tradeoff analysis can yield the greatest benefits. CebaTech’s specialty lies in the development of complex compression algorithms. Using the companies IP cores, the user can explore “what if” analysis, weighing such constraints as maximum throughput to compression ratios. These exploration efforts are enhanced by the company’s customizable IP cores.

Architectural exploration is but one half of the ESL equation. Generation of verifiable RTL code is the other. That’s the illusive goal of a complete ESL flow, namely to go from software algorithm models through to verifiable hardware. This goal will someday be realized, but probably not under the ESL moniker. At least, not according to the soft side of today’s ESL market.

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