By Ed Sperling

Design for manufacturing has been talked about for at least the past five years, but somehow it always seemed to be a problem that would be dealt with by the foundries or internally with a company’s own fabs.

 

Two things have changed since then. First, almost all companies have jettisoned their digital fabs—the remaining holdouts are IBM, Intel, Samsung, Toshiba—which means they no longer get information back on a second-by-second basis from the fab. And second, creating SoCs has become so complicated that tools are necessary to help guarantee the chips can be manufactured with decent yield to meet shrinking market windows.

 

At 45nm, DFM has become the norm. At 32nm, it will likely not even be called DFM anymore. It will simply be part of the integrated tools flow. That was the hidden message during a recent ISQED panel that looked at whether DFM was marketing hype or a secret weapon for foundries and developers. In reality it is neither. It is the formalized resurrection of a communications channel between the foundry and the design team that disappeared with the internal fab, along with some automated ways of implementing that feedback.

 

Walter Ng, vice president of design enablement alliances at Chartered Semiconductor, said his company began working in earnest with DFM at 65nm, which is about two process nodes after the hype began about design for yield and design for manufacturing.

 

Since then, virtually every sector of the system-level design industry has put its stake into DFM. Luigi Capodieci, president of Global Foundries—the AMD foundry spinoff that has backing from a United Arab Emirates venture fund—said DFM is no longer an option. It is now a requirement. That view was shared by executives at Mentor Graphics, Atmel and Virage Logic.

 

And for the skeptics who insisted for years that DFM (termed design for marketing even by some high-ranking EDA executives) was a ploy by EDA vendors to sell more software rather than bridging the communications between the front and back ends of the design process, increasingly it looks as if they were wrong.

Tags: AMD, Atmel, chartered, DFM, IBM, Intel, ISQED, Mentor Graphics, Samsung, Toshiba, Virage Logic

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