Comments on: Soft Errors Create Tough Problems http://chipdesignmag.com/sld/blog/2009/04/28/soft-errors-create-tough-problems/ Deep Insights for Chip Architects and Engineers Thu, 24 May 2012 23:22:49 +0000 hourly 1 http://wordpress.org/?v= By: BOREL Joseph http://chipdesignmag.com/sld/blog/2009/04/28/soft-errors-create-tough-problems/comment-page-1/#comment-6416 BOREL Joseph Sat, 06 Jun 2009 08:09:09 +0000 http://chipdesignmag.com/sld/?p=1041#comment-6416 Yes SOI brings a significant gain in Soft errors resistance. A 10X sensitivity order of magnitude reduction has been observed and those who have SOI components can test them at 2552 m in altitude in a platform set up I put in place near where I live. I accept contacts for further discussion. J. Borel Yes SOI brings a significant gain in Soft errors resistance.
A 10X sensitivity order of magnitude reduction has been observed and those who have SOI components can test them at 2552 m in altitude in a platform set up I put in place near where I live.

I accept contacts for further discussion.

J. Borel

]]> By: Joanne Itow http://chipdesignmag.com/sld/blog/2009/04/28/soft-errors-create-tough-problems/comment-page-1/#comment-6337 Joanne Itow Wed, 29 Apr 2009 21:18:36 +0000 http://chipdesignmag.com/sld/?p=1041#comment-6337 SOI is suppose to reduce soft error rates. Has TSMC, Actel or Xilinx investigated the potential benefit of reducing SER using SOI? What were the results? SOI is suppose to reduce soft error rates. Has TSMC, Actel or Xilinx investigated the potential benefit of reducing SER using SOI? What were the results?

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