By John Blyler and Pallab Chatterjee

Consumers love ever-smaller electronic products that have longer battery life and more features. For the chip developer, these “loves” translate to increased circuit performance and higher transistor density at lower and lower technology nodes, such as 45nm, 28nm and beyond. But these nodes are fraught with design and manufacturing challenges that weren’t really a problem at the relatively spacious geometries of 130nm and above.

As transistors shrink to deep submicron sizes and – more importantly – the interconnects between them become several hundred atoms wide, problems with parasitic effects become paramount. Designs must now gather very accurate models to extract parasitic information about resistance, capacitance and inductance in the nano-size circuit. At smaller geometrics, the effects caused by parasitics become more pronounced which means that the accurate modeling of these effects becomes more important.

Ever-shrinking margins

At older nodes – 130nm and higher – chip manufacturing was fairly straightforward. Using lithographic techniques, the design of a chip was transferred accurately to the wafer substrate. For example, when a design drew a rectilinear shape, that shape was easily printed as a rectilinear shape. If there was any slight deviation, it seldom affected the accuracy of the parasitic model.

But smaller process nodes mean smaller shapes and wire lines, which become much harder to print and etch accurately onto the silicon wafer substrate. For example, a 15% deviation in line width or a 20% change in thickness now means that when a rectangle is printed on the wafer, it might have significantly rounded corners. These errors have a profound impact on resistance, capacitance and ultimately on timing and other circuit parameters.

These lithography-related issues of printing are compounded by process and yield variations at lower nodes that could significantly change the parasitic characteristics for different regions of the wafer.

What does that mean for the system-level chip architect? “It means that designers must incorporate larger design margin windows or develop more accurate models,” notes Carey Roberston, manager for Mentor’s Calilbre xRC Extraction products. He explains that process variations and parasitics are more important than ever. With better ways to address process variations and parasitics, designers may be able to keep existing design margins or perhaps reduce the amount of required guard banding between components.

What about electro-migration?

One of the results of parasitic resistance in a circuit is electron migration. Interconnects are the narrow, thin-film metallic conductors that transport current between various devices on a chip. As geometries shrink, these interconnects get small but are still subject to increasingly high current densities. This combination of high current densities within a smaller interconnect structure can lead to electrical failure (shorts or opens) from electro migration – the transport of material via the movement of ions in a conductor.

One way to reduce electro-migration (EM) and its unwanted effects is by reducing the current in the conductors, such as lowering the power. But smaller geometries mean that the interconnect lines are shrinking in size, so that even lowering the current flow may not be enough to prevent EM.

Electro-migration doesn’t occur in semiconductors, that is, in the transistors. It is a problem in the interconnects – the lines – between devices like transistors. As these lines get smaller, parasitic resistances leads to EM or the stripping away of enough metal atoms in the conductive interconnects, which are made of metals like copper, aluminum and Tungston. But this also becomes a problem with the vias between metal layers in a chip. And today’s chips have more and more vias to connect the various metal layers.

System-in-package

If parasitics and electro-migration present serious problems for the interconnect in SoC, what about the interconnects between chip dies within a package? In some ways, system-in-package designs help to limit parasitic problems by separating the technology nodes needed for a particular subsystem, such as memory, analog and high-speed digital cores.

One of the benefits of SiP or 3D IC stacking is that you don’t need to put everything on the most advance node. “We see customers trying to break up an SoC into separate pieces to used different process nodes and then integrate everything back together,” says Robert Hoogenstryd, director of marketing at Synopsys. He explained that customers recognize that putting different types of IP – such as memory, analog or high performance digital – onto the same piece of silicon is tough. Instead, many designers are targeting each of these IP blocks onto an appropriate process node and then combining them into a stackable die system. These can eliviate some of the parasitic problems, since analog blocks often remain at high process nodes.

But the SiP approach is not without its challenges. Instead of dealing with parasitics extraction issues within a die, SiP designs must deal with parasitics on the interconnects between dies, especially using Through Silicon Vias (TSVs). Whereas traditional SiPs used wire bonding between dies, many of today’s stackable dies use TSV technology to connect the dies – drilling 50 micron vias between the dies.

“In SiPs, you have parasitic issues in the coupling between components, between die-to-die, that you didn’t have to worry about before,” notes Mentor’s Carey. He says designers can avoid some of these problems is they can implement their designs using wire bonds. But the tradeoff now shifts to performance issues inherent with wire bonds, especially those between dies – as opposed to TSVs.

Simply put, the engineer implementing a SiP design doesn’t have to worry about coupling (and hence parasitic) issues, but does have to worry about signal propagation delays. And the engineer doing TSVs between dies doesn’t have as big a propagation issue, but does coupling issues between dies.

Sparks can fly

For many years, designers have worried about unintended opens and shorts in their power line and signal circuits caused by electro-migration. Today, another much older concern has worked its way to the forefront, namely, electrostatic discharge (ESD) events. The concern is that ESD caused by a person, pin or probe touching the circuit will result a catastrophic electrostatic discharge failure. And the push to smaller process nodes increases the dire consequences of ESD events.

The real problem is not just the events themselves, but the electro-migration in an ESD protection device that may cause the device to fail. After all, the last thing you want in your ESD protection system is an unintended short to the system ground. Sparks would fly, if even on a nano-scale level.

Available tools

Many companies provide a variety of tools for parastic extraction and electro-migration modeling. What follows below is a brief outlines about some of these tools.

There are new parasitic-based RC products from Mentor, including Calibre and its PERC & eqDRC / LVS/ RC products. While Mentor’s xRC provides parastics information, their ADiT and other Fast SPICE tools can be used to do simulation of electro-migation issues.

Synopsys offers ICValidator and associated ICCompiler extraction.

Simucad has a number of extraction products that address cell- and block-level detailed device and parasitic extraction. These are based on 3D field solver models, process recipes and GDSII physical designs. The “Clever” product can produce a SPICE netlist that includes distributed RC interconnect schemes along with user defined device recognition and even contact/via vertical profile based RC values.

The newest member in the area of extraction for both RC and R is SiliconFrontline. The company was started by founders from Nassda Corp. They have a 3D field solver product “F3D” that is architected for distributed and single machine multi-core multi-thread design solutions. As such, it is a very fast product with “guaranteed accuracy” as the tables used for extraction routines are based on full 3D field equations and a fine mesh resolution. Their technology is targeted at sub 90nm processes where the reality is not really planar designs, non-rectangular vias, and device channel associated RC. One of the major features of their tool is the integration with standard device LVS flows, so the tradeoff between device recognition and interconnect does not have to be re-defined, the definitions from the “standardized and approved” tools can still be used.

Nangate has a cell builder and characterization tool for sub 65nm processes that takes into account the interconnect RC and the EM restrictions of the process. At these geometries, peak currents on minimum width line and single contact/via connections (both major sources of EM problems) can be addressed in the design specs and technology files to insure that the generated cells will yield properly. They can utilize thier own RC tool or import extracted netlists from third part tools (such as Calibre).

Tags: Mentor Graphics, Nangate, SiliconFrontline, Simucad, Synopsys

This entry was posted on Thursday, June 25th, 2009 at 11:17 am and is filed under Top Stories. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.