Who’s Doing What In China
By Ed Sperling
For anyone content to think China’s chip development is lagging at older process nodes, think again.
A survey of chip development at universities and Chinese companies, conducted by EEFocus, a China-based media partner of System-Level Design, shows nearly a third of the 34 respondents are working at 65nm with FPGA prototypes, and three of them are working below 65nm. Only one is working exclusively about 130nm.
Moreover, design sizes range up to more than 20 million gates, with the average size of the prototypes in the range of 5 million to 10 million gates. This type of chip addresses the leading edge of consumer electronics, including a variety of devices that combine voice, video and text such as smart phones. Inside China, some cell phones are being equipped with GPS and motion sensors, as well.
Perhaps more telling, only 6 of the 34 respondents said low cost was the key driver; 10 respondents said it was best performance, and another 6 said it was flexibility. In addition, 3 were being built for quality and reliability and 5 were being billed as a complete solution—something that is particularly attractive for the original design manufacturer model.
Memory in the devices is split between DDR2/DDR3 ( 9 respondents), flash ( 7 respondents) and SDRAM (7 respondents). Another four used EEPROMs.
Even the tools used to synthesize and debug are at the bleeding edge of FPGA design. More than a third are using Synopsys Synplify for synthesis, and another two are using Mentor’s FPGA tools.
Tags: Mentor Graphics, Synopsys