System-Level Design sat down to discuss mixed signal design with Robert Hum, VP and general manager of Mentor Graphics’ Deep Submicron Division; Mar Hershenson, VP of product development in Magma’s custom design business unit; Eric Filseth, CEO of Ciranova, and John Stabenow, group director for solution and product marketing at Cadence. What follows are excerpts of that conversation.

By Ed Sperling

SLD: Is there any progress in the verification of a mixed signal chip?
Filseth: Functional verification has been a challenge. It’s getting better, though.
Hershenson: Verification has come the longest way in the last 10 years. If you give an engineer $100,000 to buy any tool and ask them what they would buy, it would be a faster simulator. That’s what they want. But in analog design, simulation is not used only for verification. It’s used as part of the design cycle. In digital, there’s a clear differentiation. You write RTL, synthesize and then verify. In analog, you run an artificially high number of simulations because that’s how you design your chip.
Hum: In the digital world, the editor you use is like your simulator in the analog world. It’s your paint brush.
Hershenson: If you want a real breakthrough in analog, you have to reduce the number of simulations.
Filseth: We’ve seen people take a hammer to this problem by deliberately designing a circuit to run in two completely different technologies without resizing anything. They give up 25% area, but they say that’s an acceptable tradeoff. It reduces the amount of verification.
Hum: One thing we see in graduates coming out of school is less reluctance to use automation. Maybe their designs won’t be as good, but they’re much more willing to push the optimize button and see what happens. Maybe the tradeoff will be more area versus less design time. In the digital world that certainly happened. You can do any circuit design by hand and do better. It may take you 100 times as long and you may never get closure. In the analog world it’s been more of an optimize at all costs mentality.
Stabenow: It depends on the market. If you were doing 740 op amps then you would never make that tradeoff, because cost is everything. If you’re doing a 40,000-device SERDES on a 30 million-instance SoC, then you might well make that tradeoff.

SLD: We’re hearing about mixing older analog engineers with younger ones to come out with a better product.
Hum: There are paradigm shifts that could help. Time will tell, but there is definitely a different attitude among recent graduates.
Filseth: In classic analog design, you have to spend a dozen years before you build up the intuition to design this kind of stuff. The combination of this kind of expertise with someone who is more amenable to using tools may make sense.
Hum: In the EDA space, the lack of innovation in areas like optimization is also due to the lack of markets. You’re not going to invent something if no one is going to buy it.
Hershenson: The bulk of the work in analog optimization has been on speeding up the current flow. The fundamental problem for all these tools is that you need a good starting point for them to work. If you don’t have a good starting point, forget it.

SLD: Is there an opportunity to sell tools into this market?
Filseth: The real opportunity is to go after the 90% that’s now done manually and figure out what can be automated.
Hershenson: Optimization is not going to get you to the next level. You have to go back to abstractions and models and things that can encompass more than one job.
Filseth: The classic knock on automation tools is that it takes so long to set up the tool. You might as well do it by hand.
Stabenow: The new generation that’s coming out of school is more comfortable using these techniques. It’s a progression in analog design from the days of Fairchild until now. It takes generations to change attitudes about automation.
Stabenow: Layout tools have been around for years. The classic response is, ‘It just doesn’t look right.’ It simulates clean. But the response is, ‘It’s just ugly’ and so why use it?
Filseth: Some of it is on the tool side. But it has to be visually appealing, as well.

SLD: How important is commercial IP in this world?
Hershenson: Some people are using it for standard blocks like PLLs. But that’s not a very large percentage of the mixed signal market.
Filseth: The vast majority of mixed signal IP is in semiconductor companies.
Hum: Commercial IP is limited to areas where you don’t gain any advantage by doing it yourself. With USB 2.0, the worst thing you can do is do it yourself and get it wrong. That’s how you plug into everybody’s system, so there’s no advantage to creating it yourself. With that stuff, you go standard. The problem in the IP business is the shelf life is short and the margins are terrible. So you sell a bunch of copies, but the street price rapidly goes down.
Filseth: Lack of automation hurts that, too.
Hum: It could be that the IP industry settles out as groups of knowledgeable, experienced people who know how to do a certain thing, and analog IP becomes a service. There will be two sides of that. One side will be the standard stuff. The other side will be the embedded memory group and the power control group and the RF people.
Filseth: We think standard mixed signal IP coming out of the downturn is going to be a big deal. It’s non-differentiated IP that everybody needs. The guys who get their SoCs to market faster than the other guys are going to win.

SLD: How important is constraint-driven design?
Stabenow: We’re seeing it grow, both in importance and adoption. Maybe it’s not as fast as we would like, but the mindset that has been resistant to it is softening. If it takes longer to set the constraints up than design a circuit, then this is not of use. From a product perspective, we’re working to improve that. But then there’s also the way it’s adopted. Instead of a constraint-driven flow to produce analog synthesis, maybe it’s just the ability to have a designer at one location put intent onto the schematic electronically and a design adhere to it manually, and then have a way to reconcile that. It’s a constraint verifier approach.
Filseth: Automation and constraint-driven design go together like synthesis and RTL went together. One is an enabler for the other.
Hum: Constraints are everywhere. UPF (Unified Power Format) is a way of capturing constraints and how your power up/down stuff works. You have to capture that and get it right, but once you do that it’s easier downstream.
Filseth: The key to constraints is they have to be absolutely as simple as possible.
Hershenson: Yes, few and easy to enter.
Filseth: You want stuff that’s only related to design, too, and not the underlying technology. If you can do that, it takes you a huge step forward in portability because you’ve made your description independent of process technology.

Tags: Cadence, ciranova, Magma, Mentor Graphics

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