The Week In Review: Oct. 2
By Ed Sperling
It was the best of times, it was the worst of times, but for the overall EDA industry it was clearly the latter. For the first time in its history, EDA suffered two successive quarters of negative sales compared with the previous year. There were a few bright spots—signal integrity tools, hardware-assisted verification and resolution enhancement—but the overall market had the Dickens beaten out of it.
Intellectual property, meanwhile, had a good week. Virage Logic capitalized on its relationship with AMD—and AMD’s intense focus on its core business—introducing a new line of IP for a variety of interfaces such as PCI Express and HDMI. This also moves Virage squarely into the IBM ecosystem, where AMD is a key development partner.
Accellera, meanwhile, approved a verification IP standard best practices guide, based upon the work of its VIP technical subcommittee in May 2008. The guide provides details about how to use VIP components developed with SystemVerilog testbenches based upon both OVM and VMM. That should make the dueling parties happy—even though everyone at the standards groups insists it doesn’t matter and there is no rift between OVM and VMM.
Also in the IP world, Broadcom licensed the latest ARM Cortex A9 multiprocessor technology. In the ARM vs. Intel war, this is one place that Intel hasn’t made many inroads yet.
The Common Platform qualified Synopsys’ IC validator for 32nm design rule checking. Considering the Common Platform has been narrowing down the number of technology suppliers lately rather than offering multiple choices to chipmakers, this is significant.
Cadence updated its product line to include multicore support. That follows the Rambus-Kingston announcement last week of parallel memory. Now if only the application software could take advantage of all those cores we’d be set.
Tags: Accellera, AMD, ARM, Broadcom, Cadence, Common Platform, Kingston, rambus, Synopsys, Virage Logic