What Are They Designing?

By John Blyler

A just completed EDA tools and technology survey of 140 engineers conducted over the past several weeks shows a strong push into full-custom devices and FPGAs. In fact, 32% of the ICs being designed by engineers using EDA tools were building full custom devices, and another 24% were building FPGAs. Only 9% were working on ASICs, although the ASICs tend to be large and extremely complex chips.

About 14% were designing analog arrays and another 11% were using gate arrays. Another 10% were building ASSPs.

EDA_4Dec09_ICtype_jb_12893_image001

Share and Enjoy:

Tags: analog, ASIC, Custom Design, FPGA, Gate Array

This entry was posted on Thursday, December 17th, 2009 at 12:01 am and is filed under News Stories. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.

Comments

Resource Center

White Papers

Modernizing System Development: Requirements-based, Model-driven Design, Implementation & Test

A deep dive into the model-driven design approach to system development, which can improve system quality more quickly for a lower cost.

Hardware/Software Verification With Incisive Software Extensions

Ways to shorten the time to functionally verify software drivers along with system hardware and improve the quality of the system.

High-End Audio Made Easy: The Software Story

A look at the hardware and software challenges in audio and how to integrate audio software into Linux- and Android-based systems.

Power Benefits Of Modular Interconnect Design Using Network-On-Chip Technology

Implementing interconnects modularly enables unit-level clock gating, eliminating clock-tree switching power when no traffic is present. It also localizes logic, minimizing wire length.

Clock Concurrent Optimization

Rethinking timing optimization to target clocks and logic at the same time.

Experience With OVM-Based Mixed-Signal Verification Of The Impedance Calibration Block For A DDR Interface

A look at how Microsemi’s verification plan, its development effort and the results it achieved.

Solving The Integration Challenges Of USB-Enabled Designs

How to choose the right IP and understand the requirements imposed by smaller technology nodes, especially for the USB PHY.

Layout-Aware Diagnosis

A look at scan logic diagnosis and how it can help failure analysis engineers pinpoint the root cause of a failing die, and help yield engineers to determine the yield limiters.

Clock Concurrent Optimization

A revolutionary new approach to timing optimization, merging physical optimization into clock tree synthesis.

Virtual Prototyping For Energy-Efficient Mobile Platform Design

A deep dive into the complexity of power management at the software level for mobile devices using Linux and Android.

Community