Experts At The Table: The Past, Present And Future Of Synthesis
By Ed Sperling
System-Level Design sat down to discuss the future of synthesis with Shawn McCloud, product line director for Catapult C Synthesis as Mentor Graphics; Chris Eddington, director of marketing for system-level products at Synopsys; Bret Cline, vice president of marketing and sales at Forte Design Systems; Sanjiv Kaul, executive chairman at Oasys; and Andy Biddle, director of business development at Magma. What follows are excerpts of that conversation.
SLD: Why is high-level synthesis, which has been around for awhile, suddenly so necessary?
Kaul: In the typical chip there are multiple physical partitions. It can take a typical design team 15 hours to get through the logic synthesis portion and a week to two weeks to get through physical implementation—per block. And it can take multiple iterations through that loop. Some design teams go through that loop seven to 10 times. They’re looking for ways to get timing closure much faster, and the only way to do that is to bring physical information up earlier in the process.
Cline: That’s not the only way. High-level synthesis guys can make much better tradeoffs into the RTL schedule before it even hits a logic synthesis tool, which can eliminate a huge class of timing problems.
Kaul: You’re still dealing with RTL after that.
Cline: I agree, but we own the schedule. So if the schedule gets filled up and you go through synthesis place and route and don’t meet the timing, you can go back through the high-level synthesis tool and change the schedule. You just can’t do that in RTL. We can make the flow smoother by allowing people to not make stupid decisions in the creation of that RTL.
Eddington: That’s one of the big advantages of high-level synthesis. You iterate quickly at the architectural level and you minimize the iterations that you have to do for back-end place and route.
Cline: You should never miss timing with high-level synthesis.
Kaul: It’s not so much a question of missing timing closure. It’s how long it takes you to get there.
McCloud: High-level synthesis allows you to get to timing closure more quickly. Let’s say you’ve hand-coded an architecture that completely misses timing. The time it takes to re-code , especially if it’s a significant architectural change, could be weeks to months depending on the complexity of the design. With high-level synthesis it’s easy to adjust the percentage that you’re reserving for placement and reschedule the design. And what happens when you have a spec change late in the design? That’s a nightmare to deal with in hand-coding, but it can be dealt with relatively quickly with high-level synthesis.
Cline: In addition, the tools that are coming out at the RTL level are doing smarter things with these designs. It does make it easier for us in the long run. The things that people are happiest with using high-level synthesis, which you would never expect, are the verification improvement and the predictable timing closure. You’d expect them to say productivity.
SLD: Is there a cost for that timing closure?
Biddle: And do you see more flip-flops?
Cline: You certainly can. We have a timing address knob. You can overfill the time schedule or you can underfill it. On average, we beat a hand-coded design between 10% and 20% in terms of area and still meet timing. Generally people would worry we are larger. We’re just a compiler. We can shrink down without a penalty.
McCloud: It’s a question of how much time you want to spend on a design. We’re typically within 10%. Sometimes we’re a lot smaller. Sometimes we’re bigger. If someone wanted to spend enough time they might be able to do a better job.
Kaul: It’s not an ‘either-or’ issue. It’s an ‘and’ issue. High-level synthesis can do certain things. If you want to add a pipeline to your design or you want to change your architecture, high-level synthesis is very well suited. If you want to go from RTL to GDSII in a 28nm design, then you have to have technologies that understand what’s going on downstream.
Cline: I agree. The better the logic synthesis tools get, the better the overall results.
SLD: How accurate does synthesis have to be?
Cline: It’s different for different abstractions.
Eddington: For architectural decisions you’re leveraging the capabilities of the logic synthesis tools. The decisions you’re making aren’t exactly where you’re going to put a register but roughly how many you need and roughly where they need to go. You let the logic tool do the fine-tuning.
Kaul: It’s very design-dependent. Some designs are pushing the performance. Logic synthesis has to get you very close to where you’re going to be at the end of place and route. Otherwise you can have a lot of iterations. If your design is not pushing performance, then I think you have a lot more give.
Eddington: Logic synthesis has to be pretty accurate. You need to make better decisions at the logic level. Integration with placement is still an ongoing area of innovation and improvement. The high-level synthesis, in terms of logic accuracy in the architecture and placement of registers and so forth, doesn’t have to be quite as accurate as the RTL logic synthesis.
Cline: Our customers get a number for a baseline, run that through logic synthesis and then correlate the two. You want them to be as close as possible. After that, one of the nice things about a high-level synthesis flow is the turn is really quick—literally minutes. We don’t hear people running things for four days. If it’s running for four hours, we wonder what’s going on. That’s a curse from a licensing standpoint because you don’t run this stuff for that long. But at the end of the day, they’ll run a number 100 times and then track a number. If that number correlates with what logic synthesis would have looked like, had they run it every single time, then I think they’re generally pretty happy. It doesn’t have to be 100% correlation, but we’re not going to run logic synthesis every time because it’s fairly expensive.
McCloud: It needs to be able to give you relative comparisons. All of these tools eventually take a candidate design down through RTL synthesis to give you some accurate estimates. Once you have that, you’re comparing the candidate architecture to new ones you can create in a matter of minutes. If your candidate architecture has 150,000 gates and you have another one that has 200,000 gates, is that relative comparison correct? Our number is accurate enough to do exploration. Typically you’ve got a high-level design model that’s technology independent. You take that into an FPGA and prototype it. When you take it to ASIC, almost always you do multiple architectures. We estimate the timing and where potential timing issues will occur. The next step is to take those through RTL synthesis, and that’s when you’ll know for sure. Did it meet timing or not. The architectural exploration benefits are really the big win, along with the verification benefits—being able to do those transformations without having to change your high-level model verification.
SLD: What determines who wins in high-level synthesis?
Cline: The technology takes a bit of time to mature. It’s quite easy to synthesize a C algorithm into some RTL. That’s not a hard problem and it makes the barrier to entry look fairly low. But getting a C algorithm into RTL that’s actually manufacturable is actually quite a hard problem.
McCloud: It is centered around completeness of flow. But I would say the most important aspect is the tool that addresses the verification side of things. When you look at the RTL design flow today, 60% to 70% of the design cycle is consumed by verification. A high-level synthesis tool needs to address the verification side of that problem. The approach you take with high-level synthesis can actually complicate verification if you don’t do it right. One of the important things is to have a source description that is deterministic and predictable so you can re-use that work you’ve done in C down at the RTL level. The tool that combines synthesis and verification is the right approach.
Eddington: Both of you guys stated the obvious. A high-level synthesis tool has to deliver productivity in design. It has to deliver productivity in verification. That means reliable verification from high-level models. But right now we’re all limited by these application-specific domains. The question is how we expand beyond those.
SLD: What are the limitations?
Eddington: Mostly it’s the algorithmic guys who are adopting this.
McCloud: I think that was the case three or four years ago. That’s not the case anymore.
Cline: I would agree.
Eddington: Achieving higher levels of abstraction and having design entry environments that are tailored to the different application spaces is what’s going to help this expand a lot more. We’re doing something a little different. C is important, but we have the Matlab in the model-based stuff. That seems to work very well for designers in the system-level space who may not know RTL or C. Software engineers and video engineers know C. But other environments are needed to expand this beyond the application spaces now being addressed.
Cline: Do you worry that ability of the system designer who doesn’t understand RTL is diminished because of their lack of understanding about how the architecture is implemented?
Eddington: No. I don’t think there’s any reason you can’t have a fundamental description that’s understandable and capable of being captured by a guy who has no understanding of RTL.
Cline: We would disagree. We’ve had designs that involve a hardware engineer who knows nothing about C and someone who’s an expert software engineer who understands C to the nth degree. The hardware designer will kick their butt almost every time. The reason is that algorithms can be specified in ways that imply architectures that cannot be implemented in a reasonable amount of silicon. An H.264 implementation is a good one. You can read the data in, but data has a temporal aspect in hardware. In software it’s always there in a buffer and you just go get it. But in hardware it comes in 8 bits. What do you do with the first 8 bits?
Eddington: I agree that if you ask a software engineer to write something in a sequential language, he’s going to write something that cannot be converted into a hardware implementation without having to do some fundamental changes. In our case, we’re not doing pure language. We’re building on an approximately timed, higher-level, model-based data flow graph.
McCloud: High-level synthesis doesn’t remove the need to design. You don’t just download an MPEG-4 algorithm and push a button. It’s not a tool intended to turn software developers into hardware engineers. You still need to understand what you’re trying to create, and that’s best done by hardware designers. But what it does do is remove a lot of the details you don’t have to worry about.
