Experts At The Table: Where The Money Is
System-Level Design sat down to discuss where the value has shifted in the supply chain with Tom Quan, director at TSMC; Kalar Rajendiran, senior director of marketing at eSilicon; John Koeter, vice president of marketing in Synopsys’ solutions group, and Phil Yastrow, product marketing manager at Avago. What follows are excerpts of that conversation.
By Ed Sperling
SLD: Where is the greatest value in the SoC supply chain these days?
Quan: If you look at the last couple years from the foundry perspective, the trend is that more and more customers will select tooling along the COTS (commercial off-the-shelf) route and go fabless. They’ve handed off the wafer production to us. From our perspective we want to make sure we provide the proper value. A lot of these companies are former IDMs. They’re used to the ASIC model and they want full support and a lot of infrastructure in place. We’ve had to invest heavily in the design infrastructure side. There’s a balance when you invest heavily in wafer production and design infrastructure. We’ve got a formula to do that and still remain profitable. After the downturn the recovery has been amazingly fast.
Koeter: The semiconductor IP industry is doing very well, too. Prior to 2008 it was growing at about a 15% annual rate. It’s about $1.38 billion annually now. It’s a large segment. While 2008 was flat to down and 2009 will be down 3% to 5%, we believe it will return to a sustainable double-digit growth rate. The primary reason is that more and more people are outsourcing. The trend is toward fabless and fab-lite. Engineering staffs have been dramatically cut during the downturn, so now companies have to decide whether to do something that is difficult but which provides no differentiation or whether to just buy it from someone else. That captive-to-merchant trend is the biggest single driver in semiconductor IP.
Rajendiran: The focus is on value chain, not supply chain. Everybody should make money and everyone needs to make money because we need all the pieces to make a chip. The problem is that some areas are more profitable than others. The overall semiconductor market is not growing. The markets have fragmented from computers, to computers and communications, and then computers, communications and consumer electronics. There also are a number of sub-markets, each with a value of about $200 million, versus a single computer market that was worth billions of dollars. The way to make money is to be smart about how you leverage the investment dollars you have and where you put the money. You need to differentiate. People are fighting over each other with individual components. When the market grows, everyone can make money.
Yastrow: We’ve been making money. One of the tricks is we’re not just an IP provider. We integrate other things, whether it’s the foundry process or the package design. Integrating the IP into a customer system and helping with their channel simulations and their power—that’s where the value is shifting. It’s greater than the ASIC itself.
SLD: So is the industry aggregating or disaggregating?
Yastrow: There’s more disaggregation of the pieces, but there’s aggregation of the people who pull together the pieces in a cost-effective way. When we were part of Hewlett-Packard we owned all of our own fabs. Now we go to TSMC. We’ve disaggregated from that point of view.
Quan: One of the advantages of disaggregation is that everyone can focus on their part. But we also see a lot of duplication and waste. There are a lot of companies developing a piece that are not looking across the ecosystem to see another piece that it needs to work with. Last year when we launched our Open Innovation Platform we talked about how to collaborate across the supply chain so you don’t have to duplicate efforts. Part of the value chain isn’t just about getting the customer to pay for what you’re developing. It’s also about reducing the cost of what you develop and delivering the piece you’re supposed to deliver. If you reduce cost and duplication, each part hopefully makes money.
Koeter: It depends on the market and the applications the customer is in, too. If you look at areas like Israel and China there is continuous disaggregation. If you look at Japan, there is a trend toward re-aggregation. Companies that have been going to COTS are heading back to ASICs. And North America has always been a do-it-yourself region. It also depends on the applications area. Systems companies like Cisco and Nokia that used to do their own ASICs are moving to a straight ASIC handoff or, ‘Here are my requirements.’ Nokia has totally exited chip design. This is more true in the digital world, though.
SLD: What’s happening in analog?
Yastrow: There is definitely less disaggregation in the analog world.
Quan: Some of the big IDMs like Texas Instruments and ST, as they go fab lite and move some of their designs to foundries, retain their core competency in analog. Most of the baseband digital is moving to the foundries, but they want to make sure their core competency in analog is not compromised.
Koeter: Recently we acquired the MIPS analog business group, formerly Chipidea. One of the reasons was to convince people that what used to be on a discrete chip can be successfully integrated on a mixed-signal chip. That’s challenging, though. It involves 1.8-volt architectures and low-threshold transistors. It’s not easy. We’re putting a lot of intellectual horsepower into solving those issues.
Rajendiran: As complexity increases, whether it’s analog or digital, disaggregation will happen. There will be specialty companies that will appear. If you go back in the history of semiconductors, companies were vertically integrated. As complexity grows disaggregation will happen. Bell Labs is gone. IBM doesn’t do as much basic research as it used to do. But along with that there’s also re-aggregation. Just having a wafer doesn’t mean much. You have to sell an iPhone. Both aggregation and disaggregation will always exist.
Yastrow: I think we’re re-aggregating at a higher level than we’re disaggregating. In the 1980s HP computer boards were so complicated no one in the world could build them. It didn’t take long before companies like Celestica came along and disaggregated them at that level. From a chip design point of view, everything was an ASIC because timing and place-and-route were so complicated. Then you started to see COTS popping up. You were able to disaggregate at that level and outsource. Then there are companies taking the pieces and the package-tested parts and re-aggregating at a higher level. You’re seeing different levels of activity at different levels of the value chain.
SLD: Is the value higher at the bleeding edge of Moore’s Law now than it was a couple nodes ago?
Yastrow: You might get less because there are fewer chips and more stuff on each chip.
Quan: If you look at 32nm and 28nm, certainly the cost of building the fab is humongous. It’s now about $4 billion to $5 billion. There are fewer designs even though the designs are more complex. The older nodes—0.18 and 0.13 (micron)—are more mainstream. That’s where the derivative stuff is being built—analog, high-voltage, high power, DMOS, CMOS. Those continue to add value and customers continue to build products around that. The value continues to increase across the board, though. Some chips require an analog front end or an RF front end that don’t require a 40nm or 28nm process. There’s a mix, and the value depends on what you’re building. From a wafer perspective, we continue to see demand across the board.
SLD: But is the value really as great as it was when the bleeding edge was 90nm and some companies were at 180nm?
Quan: We still see large fabless companies leverage the advanced node for higher performance, lower cost and lower power. But the rest of the industry is not necessarily following that as fast as before. The complexity and the cost are too high.
Koeter: We see most every design that’s going down in the industry and we keep a master list of those designs. That’s at the highest level of security in our company. Only two people ever get to see it. From that we track the time to the first 500 tapeouts. From 130, 90 and 65, every one of those was exactly two years. At 40nm it hasn’t gotten to 500 yet. We haven’t had 500 design starts to tapeout. It will be about 2-1/2 years at 40nm. Migrations to new technologies are definitely slowing down. But from a value standpoint, because people are going fabless, the value of an IP provider is quite high.
Tags: Avago, eSilicon, supply chain, Synopsys, TSMC