The ARC Video Subsystem
Video coding systems are a cornerstone of portable, media-centric devices. This paper introduces the Virage Logic ARC Video media subsystem, which decodes all major video- coding standards including H.264, VC-1, MPEG-2 and MPEG-4 Simple and Advanced Simple profiles. The low-power, silicon-efficient, high-performance subsystem contains a 7-stage pipelined RISC processor, a 128-bit SIMD processor, a 2D DMA engine and an entropy decode accelerator. ARC delivers the subsystem as IP, which can readily be integrated into video- enabled system-on-chip devices.
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Tags: Virage Logic











