The Week In Review: Jan. 29
By Ed Sperling
Mentor Graphics added SystemC support to its high-level synthesis Catapult C, basically trumping the competition in the HLS space. The advantage is that you can now run synthesis in the same language as high-level modeling. But given this is a game of leapfrog, don’t count on this lead to stay untouched.
Toshiba Information Systems standardized on Synopsys’ VMM-LP methodology, scoring one for the VMM side in what is often a contentious “non-war” between the non-rival verification methodologies OVM and VMM. And where is UVM in all of this?
Synopsys also expanded its IP portfolio with new 3G DigRF and Camera Serial Interface 2 controllers, and PHY for the Mobile Industry Processor Interface.
Atrenta inked a deal to develop an EDA tool quality management system with the Semiconductor Technology Academic Research Center in Japan. As part of the arrangement, STARC provided regression test specs and test cases to Atrenta, which has integrated them into its SpyGlass test suite. STARC cut another deal with Cadence along similar lines.
In the standards world, Actel is now in compliance with the rigorous ISO 9001 and SAE/AS9100 standards, which mean its chips are now qualified for the most extreme conditions imaginable–and then some.
Ever wonder why Intel decided to build all those fabs in the desert? Check out the eight new solar operations the company is planning. Expected power generation is about 2.5 megawatts. Who needs power companies?
TSMC’s Q4 revenue increased 43% compared with the same quarter last year and net income increased 163%. That’s a lot of zeros in the right place. Either they were giving away wafers last year during the downturn or the number of companies developing chips at advanced nodes is way, way up.
Tags: Actel, Atrenta, Intel, Mentor Graphics, STARC, Synopsys, TSMC