Experts At The Table: Where The Money Is
By Ed Sperling
System-Level Design sat down to discuss where the value has shifted in the supply chain with Tom Quan, director at TSMC; Kalar Rajendiran, senior director of marketing at eSilicon; John Koeter, vice president of marketing in Synopsys’ solutions group, and Phil Yastrow, product marketing manager at Avago. What follows are excerpts of that conversation.
SLD: How much of the value is in lowering energy consumption?
Quan: If you have an iPhone today, it probably lasts seven or eight hours of normal use. In a few years, it might last a few weeks. You have to have a lot of different ways to shut things down.
Koeter: It’s partially application-driven. It’s also process-driven. The most advanced processes are pretty leaky. If you combine that with more and more transistors it’s becoming a bigger issue.
Quan: Yes, that’s definitely the trend. If you draw the polygon smaller and smaller, just because a physics it’s leakier. Now, if you multiply that times 1 billion transistors, it’s going to be a lot leakier. The design side will need to continue to improve to save power. From our perspective, power will continue to be where the value is. For us, it’s power, performance and area—PPA. The first ‘P’ is now power and it has been since 40nm. Very few people care about area. If they can hit the performance spec and the power spec, they worry about area later.
Koeter: We just did a study in which we found that 65% of designers say that low power is the No. 1 challenge. For the first time it exceeded timing closure.
Rajendiran: Power is part of the consumerization of everything. When people carry a device in their pocket they want to reduce the leakage and prolong the battery life. But equally important—and becoming more important—are the number of switches and routers. They are increasing every day. Systems designers don’t want to change the chassis but they do want to increase the number of ports. We are not talking about leakage power here. We’re talking about active power. People who can supply a product that can address lower active power in a data center can get more value because businesses can provide more than a consumer. Even if it’s a USB, from one IP vendor to the next one may have more power down modes than another even though it’s a standard. There’s a lot of value IP providers can bring into the picture. It’s the same with SerDes. You can have 100 of them, and if you reduce each one by 100 milliwatts it pays big dividends.
SLD: But it doesn’t necessarily mean you’re making more money if you’re providing more value, right?
Yastrow: The revenues go down because of Moore’s Law, even though you’re putting more things into a design. But the place you’ll see the hockey-stick ramp in revenue is if you start pulling memory onto a chip. Right now a networking company spends X dollars on ASICs and X dollars on external memory. If you can combine them, whether it’s through a stacked die or a high-speed link between the two, you can capture more revenue.
SLD: Does the value shift as we move down over the next couple nodes? At 65nm, the value was in the hands of designers. Now, with restrictive design rules, it seems as if it’s moving into the architecture and the integration.
Yastrow: You need everyone to keep getting better. Whether you’re designing at the logic or the physical level, it’s still a challenge. I don’t see one of the jobs getting easier.
SLD: But is it the same job, or has it moved from design engineer to systems engineer?
Koeter: Over time, it’s going to be the latter. We just had a meeting with one of our major Japanese customers. They were presenting figures that on a major project today they have 20 RTL designers. They said in five years they want 4 RTL designers and 16 software architecture guys. Whether that will be a reality is unknown, but that’s their goal. The goal of most semiconductor companies is to move up, so someone has to fill the gap. That’s where a value chain producer like eSilicon can provide a huge value.
Yastrow: There might be shifts in the number of people. There may be fewer RTL people and more architects trying to cleverly craft things so we can use this kind of memory vs. this kind of memory to save bandwidth or area. But the people at the transistor level are having to increase their knowledge, too. It’s all becoming harder. There is some shift. There are new architectural techniques to re-use pieces, but everyone is moving up.
Rajendiran: There will be an overall trend toward architecture and market definition that will occur more because of business reasons than technology reasons. There are going to be more restrictive rules if 3D chips don’t become a reality. If they do become reality, IP will be impacted because there will be a lot more floor planning needed. Some parts of the design chain will benefit more quickly than others depending upon the direction this takes, but overall there will be more emphasis on defining the right product.
Koeter: It’s a huge opportunity for EDA to enable automation at the system level and through to RTL, as well as for IP. IP has been getting much more complex. There’s no doubt in our minds at Synopsys that the next step for IP will be integration into what we call subsystems. People will want configured IP subsystems for audio, video or graphics, for example.
Quan: You also need the ability to optimize or reduce the cost of the infrastructure. You get more profitability if you can reduce your design costs or infrastructure costs. A lot of customers and designers are moving up the value chain. They’re doing more systems and software. Someone has to fill in the gap. There are the value chain producers. But there also are libraries to validate the silicon IP, and the flows and tools all have to be pre-validated so customers don’t have to test all the tools. Also, the quality built into all of these components has to be higher so you have a better chance to get to silicon quicker. If you can get to product in one or two spins while your competitor requires three or four spins, that’s a huge competitive advantage. It’s not just to tapeout. It’s post-tapeout, first production run.
SLD: Is it the technology or the business model that makes the difference?
Rajendiran: The technology companies are providing more and more value. That’s their path. But is the end customer getting the value out of what you’re producing? You can pack as much technology as possible into a 40nm chip, which is a lot more than at 90nm, but is the end customer benefiting from that? That’s really the question. If you’re doing one or two products, you don’t have the time to learn everything that’s going into a product and then extract it. Then it becomes a business model question. Who can fully take advantage of the technology being developed from companies like Avago or Synopsys or TSMC, and then who can bring it to the end customer? You need to extract more than the individual components.
Yastrow: I think the answer is neither. With a strong shift toward a consumer-oriented, semiconductor-driven world there are different things they care about. It’s not the most megahertz. It’s having a good solution at the time the market needs it. That doesn’t necessarily fall into technology or business. It falls into whether you provide a solution with the right features as a cost-competitive point. That talks directly to schedule and risk, which is one of the driving forces for an IP vendor.
SLD: That sounds like a business issue.
Yastrow: I think of a business issue as one between to commercial parties. But in this context, yes.
Quan: We have a few large customers and a lot of small ones. We face this question everyday because of all the startups that get their first funding. That’s more the business model. More and more we see startups with limited funding. They can’t afford to have a CAD team and validate every single tool because time to market requires them to have a chip to market at a certain time. There’s no way they can everything themselves. That’s how the small company can compete with the big company. We have a few hundred of these emerging accounts worldwide. A lot of their success or failure depends on how they manage their initial investments in the infrastructure.
Koeter: We saw the same thing and came up with the Ly-nx design system.
Yastrow: It’s still the same theme. We’re disaggregating a lot of the lower-level technology because other people can do it better. At the business model level, we’re aggregating. We’re not so concerned about the TSMC wafers or Kyocera packages. We’ve handed that off to someone who knows how to do it. And we’re thinking of clever ways to turn that into something useful.
