Experts At The Table: The State Of EDA
By Ed Sperling
System-Level Design sat down with Antun Domic, senior vice president and general manager of Synopsys’ Implementation Group; Serge Leef, vice president of new ventures and general manager of the System-Level Engineering Division at Mentor Graphics; John Busco, CAD manager and blogger, and Sanjiv Kaul, executive chairman at Oasys. What follows are excerpts of that conversation.
SLD: Where is EDA today? Is it more valuable than it used to be?
Leef: EDA user crossroads right now, which has to do with what’s happening with our customers. The group of customers we historically have served is dividing into two camps. One group is doing huge, very complex platform chips. They need sophisticated back-end flow tools, as well as sophisticated front-end tools that allow them to model and experiment with sophisticated 500 million-gate designs. The process for those people is being strained on both edges. However, there are fewer and fewer people that can afford to do huge chips like this, and certainly fewer that can afford to manufacture them. The second group that is emerging and becoming much more prominent is the group that does systems. Their challenge is to take those systems and add value to them, whether it’s through software or industrial design or packaging. The community that’s emerging includes system designers, for whom the large, vertically focused platform chips are becoming more adequate. The motivation for them to do original hardware declines. But they do have to solve system-design problems.
Kaul: You can’t get a chip designed without EDA, and chip design is still very important to our economy. But if you do an analysis on the EDA industry, its competitive position is diminishing. There are fewer people doing these big chips. There is less differentiation between the EDA players. Some would argue there are too many EDA players, and therefore the differentiation is less and the negotiating power of the EDA players is diminished. If you talk to EDA companies, they think they’re not getting enough value for what they produce. It’s more a structure of the industry, with regard to the customers and the competitive position of the industry.
Leef: The trend of the separation of the design community means the EDA industry is having a hard time satisfying the platform chip designers because they really are pushing the state of the art. At the same time, they don’t know what to do about the system-level designers. We have one market that’s diminishing in size but growing in complexity, and then we have this other market that is potentially large but we don’t know how to tap it.
SLD: What’s the user perspective?
Busco: Of course EDA is important, but the value is splitting because the way the design community is getting strung out over many generations of silicon. For people that are still willing to design ASICs for their application at 130nm, or even FPGAs, EDA is necessary. But it’s more of a commodity product. If you’re designing at 40nm 32nm or 28nm, EDA is not only important, it’s incredibly valuable. You can’t do you design without it. That market is getting smaller because the NRE costs are becoming such a high hurdle that many companies cannot justify the design. But for those that can justify it, EDA is just as valuable as it was in the past.
Domic: There are people doing very important and profitable designs at 130nm, and there are people moving to 28nm. The spread is much larger than it used to be. I don’t need the latest signal integrity analysis tools if I’m going to be doing another 130nm derivative. On the other hand, I see that even with the decrease of the number of very large chips, the number of licenses we see being consumed by our customers continues to go up. Going to 32nm and 28nm and forward, we’re finally getting to the point where the only ones able to make the investment will be two or three [EDA] companies. Startups tend to go for not even a tool but a subset of a tool. To design a 100 million-cell chip, very few companies can do it.
SLD: We’re coming at this from two perspectives. One is from the user, the other is from the EDA company.
Domic: But if someone today wants to provide a full place-and-route solution with all the parasitic extraction, DRC and LVS, the R&D investment EDA companies need to make is enormous. You can’t invest more than 30% or 35% of your sales in R&D or Wall Street will question your existence. So we’re seeing a similar problem in EDA. A customer cannot just say they’ll design a 50 million-cell chip. EDA is seeing the same problem. They have to be selective about where they develop their tools.
Kaul: One of the challenges for EDA has been that with new technologies it doesn’t take a very large team to build the technology. Most successful products were built by four or five brilliant guys. Obviously the first release of the product has to have enough value that people will buy it, and the bar can go higher and higher as you move into more complex technologies. But that’s one of the reasons there has been more competition in EDA than is probably healthy.
SLD: Will that continue?
Kaul: As long as the current solutions are not meeting the needs of customers—if it takes five days to run place-and-route on a complex block, for example—there is an opportunity for someone to come in with a better solution. If you need 20,000 servers to run simulation and you’d like to see a 20x improvement, there’s an opportunity. It’s not easy, but it’s what you have to do.
Leef: When I started working at Intel in 1982, they believed the reason they would win was architectural superiority, their ability to push the state of the art in process, and because of their CAD tools. At that time, the EDA landscape was pretty bare and Intel had 300 to 400 people working on EDA tools. It was predicated on the fact that Intel didn’t believe anyone outside of Intel understood their problem well enough to solve it for them. At 22nm, Intel once again believes no one else understands its problem. It’s not inconceivable we might start seeing big semiconductor players bringing EDA back in house.
Kaul: IBM already uses a lot of internal tools.
Domic: It’s more complicated than that. Every quarter Synopsys announces we had one customer that contributed more than 10% of our revenue. At the same time, the internal team than what they had for EDA is larger. I don’t see a return to internal tools, but I do see a combination where they work with a few suppliers in specific areas, and those areas may change in time.
Leef: But if Intel decided one day that it was important enough to distinguish itself with EDA, that could have a big effect. It’s not economically challenging for them.
Domic: Nobody has money to do everything.
Busco: There will continue to be innovation by startups and small shops. It’s something that everyone benefits from. EDA is an academically rigorous and exciting field, so there are a lot of extremely bright people going into these areas. They’re anxious to start up a company with a small team, and we see the benefits. There are needs for new point tools. Some of the existing tools can’t keep up with design sizes or process complexities. Either the point tools from these startups will solve the problem or they will wake up the major players, which is a side benefit. The major players have a strong tendency to become complacent or focus their efforts elsewhere. When a startup shows them that something can be done in a revolutionary way either the startup will walk away with the business or the established player will turn the battleship and come up with a much better product, as well.
SLD: At 28nm and below, are the big chipmakers relying on internally developed tools until the other stuff becomes commercially available?
Busco: It depends on the style of designs. For digital ICs, commercial EDA comprises the vast majority of the solution. Companies have CAD groups to integrate flows and develop point tools where they can add value, but a customer will not write anything like a place-and-route or synthesis tool. Back when signal integrity was a novelty, we may have had to develop our own tricks. But now it’s part of every EDA tool, so there’s no need to develop an in-house solution.
Kaul: Whatever EDA can solve, customers will buy commercially. But EDA companies also have to make business decisions. They try to solve problems they think will give them a competitive advantage or which they can make a business out of. There are certain problems where the data required to make a good product is proprietary. Intel and IBM don’t want to share that with you. They’ll develop it themselves. Either that or the EDA companies don’t want to solve the problem for them because it makes no sense economically. But if these companies can buy commercially, it’s less expensive.
Domic: If you look at innovation at the large companies, Mentor and Synopsys have done a good job providing things that didn’t exist like, lithography checks. Everybody did chip layouts, even though to keep up with the set of rules at 28nm is tough. But when you look at lithography checks, we built a completely new router that will carry us to 28nm and 22nm. When I do see internal efforts, it’s because there is a lot of flux in terms of preferred rules. Every company interested in coming out early with a new technology is doing their own schemes to develop what is important and what isn’t. The investment from the large companies has been pretty significant and has managed to satisfy IC developers. I don’t see many people trying to develop their own lithography checker.
Leef: In the areas where the tool footprint is well defined, the major EDA vendors jump in, invest heavily and come up with good solutions. In areas where the footprint of the tool and the definition of the need are fuzzy, that’s where the customers have a tendency to invest their internal cycles and do things specific to them. But if you’re architecting a chip with 500 million gates, the architectural and system-level alternatives are profound and the EDA industry has not come up with a cohesive set of tool footprints in that area. Almost every customer I talk with that’s trying to solve front-end problems has a home-cooked solution or some combination of commercial, public domain and home-cooked. The boundaries between what the commercial tools can provide and what the in-house tools can provide are fluid, and that’s where we see internal EDA groups putting a lot of effort.
Tags: EDA, Mentor Graphics, Oasys, Synopsys, System-Level Design