System Verilog appears heading for some serious overhauling. Mentor’s Dave Rich says there were 472 updates to the latest Language Reference Manual, along with 986 open issues.

Along the same lines, there’s another interesting note about extensions to the language at the tail end of a blog on the Synopsys site by Vishal Namshiker of Brocade and Srinivasan Venkataramanan from CVC Pvt. Ltd.

So what does this all mean to verification engineers? A panel at DVCon, as reported by Cadence’s Richard Goering, focused on things that keep verification engineers awake at night. In our humble opinion it’s better to be sleepless and think about  solutions than to wake up screaming. What would the neighbors think?

Mentor’s Jon McDonald addresses irrational expectations vs. reality in high-level design. The bottom line is garbage in yields garbage out. That may be the most important equation to ever hit the ESL world.

Si2’s Steve Schulz looks into process design kit standards and why they’re so important—and why PDK standards are so hard to create.

Tets Maniwa drills into the annual EDA Consortium’s CEO forecast panel on Gabe Moretti’s Gabe on EDA site. It’s a good representation of the view from the top.

What exactly is real time? It depends upon where you go for the definition. As Mentor’s Colin Walls points out, the answer isn’t as obvious as it sounds.

Harry Gries has a photo that should not be missed, and his blog is certainly worth reading, too. It’s about radically rethinking projects. That’s been a common theme lately on all sides of chip design.

Mentor’s Steve Collis brings up an interesting analogy. If it’s easier to consume less food than to work it off at the gym, then shouldn’t the same apply to consumer electronics? This could be a literal interpretation of food for thought.

Daniel Nenni jumps into the comparisons between the major foundries—TSMC, GlobalFoundries and IBM. There’s a particularly interesting note in there about 40nm tapeouts. More than 60 customers have taped out chips at that process node at TSMC. There’s also some interesting information about interconnects, insulation and changing the resistance of copper.

Mentor’s Thomas Bollaert looks at a post from Synopsys’ Frank Schirrmeister and says it will be quite some time before chips are an assemblage of IP blocks. Sounds like a challenge. Pistols at dawn?

Tags: Cadence, ESL, GlobalFoundries, IBM, Mentor Graphics, Si2, Synopsys, TSMC

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