Experts At The Table: The State Of EDA
By Ed Sperling
System-Level Design sat down with Antun Domic, senior vice president and general manager of Synopsys’ Implementation Group; Serge Leef, vice president of new ventures and general manager of the System-Level Engineering Division at Mentor Graphics; John Busco, CAD manager and blogger, and Sanjiv Kaul, executive chairman at Oasys. What follows are excerpts of that conversation.
SLD: Is communication between hardware and software engineers improving?
Leef: The system guys see the problem as a software problem. But a hardware-oriented language like SystemC makes no sense to the software guys. They have no notion of concurrency or time. I have not, to this day, seen a single software guy that would willingly develop something in SystemC that could be embedded. SystemVerilog is even further away from that. What you’re doing is raising abstraction for the hardware guys, but we’re not doing anything for the entire system.
SLD: Do we need to train engineers differently, and if so, how do you get there?
Leef: My opinion is yes, because the majority of jobs are going to be in systems. In 1982, there were less than 5,000 people in the world who knew how to design a chip. That hasn’t changed much today.
Kaul: Are you saying there are the same number of chip designers and then an additional number of system designers, and that there will be more people becoming system designers than chip designers?
Leef: Yes, the latter. And my theory is that in the mid-1980s, almost everyone worked for PC chipset companies. There was a processor and a lot of other chips. Today, there is a processor and a graphics processor and not much else. There’s been a giant sucking sound on the motherboard. The same thing is happening with smart phones. There are three or four designs that are perfectly adequate, and not much separates one from the next.
Domic: But if you look at the majority of these smart phone manufacturers, they don’t design ICs.
Leef: There will always be opportunities for really smart chip designers, but there will be fewer and fewer of them.
Domic: But then the question is, who is going to provide the software? If you look at the investment Mentor or Synopsys makes, it has kept increasing. But it is not the majority of our investment.
Leef: That’s because we haven’t figured out what is the successful tool footprint in that space.
Domic: Or maybe somebody else will do it.
SLD: Are engineers making this shift from RTL to system-level engineer?
Busco: If you’re at one of these surviving companies that is still making chips, there is plenty of demand for RTL designers who understand deep submicron effects and who can guide the chip through physical design and take into account cross-talk. I haven’t really seen the migration yet. It’s logical that there will be so few companies capable of building chips that they’ll have their massive staff of chip designers and other people will use those as components. But I haven’t noticed a strong trend.
Leef: You won’t see it, but if you go to one of your top mobile customers, about three years ago they decided they were no longer adding value in the silicon platform. They are adding value in software and radios. Their business hasn’t fluctuated because of that.
Kaul: The group sitting around this table is biased toward standard cells. A lot of people are developing FPGAs, and we don’t see them that much. But there are more gates being designed for FPGAs. If you measure gates being designed these days, Xilinx might be the No. 1 customer of EDA. It’s a different pathway. FPGAs have become much more cost effective. It’s still RTL design, but it doesn’t have all the challenges of getting to silicon.
Leef: There are different ways to get into FPGAs, though. Some people are coming down from ASICs. They have methodologies that are traditional from our perspective. It’s just the very last step that is different. There are others coming to FPGAs from lower sophistication and from software. Those people do not believe they need EDA tools, because what Xilinx provides plus MatLab may be sufficient.
Kaul: The tools that Xilinx provides are EDA tools. But they’re given away for free as part of selling the silicon.
Busco: You mentioned the trend of systems companies moving away from chip design. In general, that’s true. But the exception is Apple. They’ve acquired companies, they’re hiring people, and they have a different perspective.
Leef: Apple is the exception that proves the rule. They always go against the flow.
Domic: We’re more concerned about the complexity than an inductive effect of the fourth order that becomes second order. We’re good at taking care of those things eventually, but one part that is becoming worrisome is the completion of the RTL and the level that the tools can take it to effectively—that completion point is taking longer and longer. We have been forced to modify tools. Engineers get clever at ignoring stuff. They may say, ‘This IP is not complete so I’m going to ignore this.’ There is a point where you’re going to have to work with very incomplete data, and to be able to proceed with the design. You can’t have the rest of the team waiting until the RTL guys have run enough regression that they can say it is safe enough to proceed. The tools have to deal more with this level of uncertainty and to produce some data. One part may be very clean and another may not. We’re connecting logic synthesis to design planning so people can see a little better what is happening. That may create a new evolution in the tools. It doesn’t go all the way to system, but it’s clearly different from what we have seen.
SLD: This is a leap of faith based upon the tools that high-level models require, right?
Domic: Yes, it’s along those lines. The difference is that the expectation is the rest of the data will be completed within the next few months, but enough has been done to say this floor plan will be okay so you can proceed to do this piece once the real data is presented. Working with this incomplete data—some people call it dirty data—and being able to derive good conclusions from that incomplete data may be a new direction for EDA tools.
Busco: That is the reality of design. Everything is not finished at the same time.
Domic: But there are also design compilers that try to take things to the letter.
Busco: Yes, and if it sees a timing violation it’s not going to look at anything else. It’s going to obsess about it.
Domic: What we need to do is get it to ignore certain things. It’s being able to proceed with uncertainty in synthesis, place-and-route and synthesis and timing analysis when you know there will be another netlist every three days. But we also have to do it cleverly so people can use the results effectively. That’s a challenge.
SLD: Does 3D stacking change the model and redefine the problem so not everything has to be at the most advanced process node?
Domic: If it works out like that, then yes. It’s not that everyone is going to use 28nm to divide something among 10 chips. People are going to use that because something works well at 130nm and they don’t want to re-do it. In that case, the changes are smaller and the traditional EDA tools, with extensions, will do a good job. If you want to create everything from scratch and divide it among 10 chips, then the game will change very dramatically.
Kaul: If you go to 28nm you’re going to have so much capacity that everything will fit on the chip. The advantage of 3D is being able to use older technologies. Going to a 28nm node is very expensive. It costs a lot of money to get there.
Domic: The analog design always lags.
Busco: So does DRAM.
Domic: Yes. And it will be a very natural extension.
Leef: I was on the advisory board of a fabless semiconductor company, which was doing an array of cores on a massively parallel chip. They made a conscious decision to use 130nm because they would have enough money to go through four tapeouts. From a monetary standpoint there were no benefits to going to more advanced process nodes.
Busco: Graphics is embarrassingly parallel and Moore’s Law is a friend. But the economics may say, ‘Why be on the bleeding edge. It’s not justified.’
Tags: Mentor Graphics, Oasys, Synopsys