System-Level Design sat down with Glen Daves, director for packaging solutions development at Freescale Semiconductor; Carey Robertson, product marketing director for Calibre Design Solutions at Mentor Graphics, Rajiv Maheshwary, senior director of customer marketing at Synopsys and head of the company’s 3D initiative; Javier DeLaCruz, director of semiconductor packaging at eSilicon. What follows are excerpts of that discussion.

SLD: Is 3D really going to happen?
Robertson: Based on what our customers are saying, it definitely is real. It’s applicable to certain designs such as memory already. And we’re starting to create multiple cores with memories on top. That’s driving a lot of tools effort. We’re definitely seeing the investment. We’re not ready to predict it will be ubiquitous, but it’s beyond test-development.
Maheshwary: It is real, but it’s going to take some time. We are hearing three major reasons why people are looking at 3D, and there is proof in each in terms of demonstrator chips. The first reason is form factor, and the proof there is CMOS image sensors, which have been in production since 2009. Along the same lines, people are looking at the tradeoffs in memory stacking. That will go into production late this year. The second reason is heterogeneous integration. That’s performance-and power-driven. Memory bandwidth is a big issue, especially with logic and multicore processors. The timeline for that is probably around 2012. The third reason is that customers are experimenting with the IP, time-to-market and cost of mixed-signal SoCs. If you can separate the analog functionality and move it to another chip, so you can have the analog functionality at 130nm and a digital chip at 65nm or 45nm, then you can get an advantage in time to market.
Daves: The key question is what kind of 3D we’re talking about. Chip stacks are already in production, and we’re seeing dual-sided packages, mostly driven by miniaturization. But as we move into 3D with TSVs (through-silicon vias), it’s all about performance. You can build a device with TSV technology you can’t build any other way. For massive bandwidth, how do you get 10,000 or 100,000 connections between two chips? And there are certain high-speed applications where TSV technology is a real enabler. The technology is real and we’re absolutely pursuing it.
DeLaCruz: Companies need some form of differentiation for their products. That can come down to cost, miniaturization, speed, performance, or a number of things, and 3D is one avenue to get down to that path. Wire-bonded 3D has been around for years, and it has primarily been driven by space. Up until about a year ago, it was more expensive to put two die in one package than to package them separately and put them on the same board. Once we crossed that point, assuming you’re in the same technology it now makes sense.

SLD: What’s the technical hurdle we have to solve?
DeLaCruz: In stacking wire-bond die, it’s pretty straightforward. You use the same architecture. You have buffers on the edge of your die, wires bonding to each other, and it works well. TSVs are completely different. There are a lot of advantages of using two die next to each other, but there’s no reason to drive memory from one die to another using 1.8 volts or 2.5 volts. There is very little resistance, much lower parasitics to running them off the same core voltage. The IP doesn’t exist. If we were able to do that, we would be able to get to very low power. You don’t need all that voltage to drive a chip.
Maheshwary: There are some business issues and there are some technical issues. From the business side, it’s a bit of a mess. People have so many choices and flavors. We need to be quite pragmatic about what really works. Over the last year we’ve been researching this and injecting some sanity into it. There were all the fab flavors—via early, via middle, via last. There also were all the bound-up flavors of chip to chip, die to wafer and wafer to wafer. The number of choices we’ve given engineers is enormous. We’ve got to be more pragmatic in terms of what it is that you really want to build. That’s why larger companies, which have proven this technology—companies like IBM and Intel—don’t have the right applications to launch it. There are technical challenges, as well. If you look the reliability and the stress analysis of TSVs, we don’t have a lot of data. What are the rules when you have a TSV vs. an active device? Can you keep it within 5 microns? Can you keep it within 20 microns? How is it going to impact the device performance. We are doing a lot of research in that area. Another issue is around test. What test do you use? Do you use JTAG for die level or package level? What about stack testing?
Robertson: It’s a question of, ‘Can we collect industry best practices?’ There are different technologies on the manufacturing side with different via technologies. There are also different design methodologies. Are we going to put memories above cores and strictly look at the design techniques, putting analog in one place and digital in another? That makes it nice to partition the design, but then there are others who want to do path analysis across these dies. Are there portions of functionality now spanning multiple dies? There are specific design methodology issues. And if we’re talking about TSVs, we’ve been wrestling with stress on the silicon for several generations now. These TSVs use thinner wafers, so the stress for individual MOSFETS is different. We also have to think about thermal and how we’re going to dissipate heat now that we’ve stacked up all these chips. And for many designers, these TSV components are inductive. They’re going to have a profound effect on the magnetic fields within a die and surrounding die. Not many designers are considering inductive effects even within their own chip. Now we have the potential for noise issues between chips. There are significant modeling challenges ahead.
Daves: There’s also ESD (electrostatic discharge association) protection. When you have a bunch of I/Os and TSVs, there isn’t enough space to put ESD protection on every I/O. The other challenge is that in the design realm, when you have a circuit that is cutting across pieces of silicon—and a 3D circuit is really the end goal—we have a long way to go before we have tools that can support that structure and lay it out.

SLD: One of the big advantages of 3D stacking is the ability to run different technologies on a chip. Sometimes it involves different voltages, sometimes it’s completely different protocols. How do you solve the integration?
DeLaCruz: Years ago you could design your die with complete isolation from downstream processes. As you get to higher levels of integration, especially when you have multiple chips, you have to design from the system down to your chip. That could be a backward flow. Knowing what you need to connect to, at what speed, and then even before you do floor planning for the chips, how they are going to connect to each other are critical. Right now memory is cheap, but they’re bonded along the middle of the die because that’s how they’re packaged. To put them in another device you will either need extremely long wire bonds, which causes cross-talk, or you will have to put them side by side and the pads will need to match from the very beginning. You really can’t design these die in isolation. If you’re doing die-to-die connections with TSVs, you need a physical design tool to do that and you add a lot of your own customization. But if the connection requires some assembly—putting two die on opposite sides of the package, then it becomes the packaging tool’s responsibility. A lot of these EDA tools still have the old mentality of, ‘It’s a die problem, it’s a package problem, or it’s a board-level problem.’ This is a problem that includes all of them.
Daves: There are many applications shipping today with integration of dissimilar technologies in a single package. At Freescale we make tire-pressure monitor sensors. There’s an analog chip, an RF chip, a pressure sensor and a microcontroller. Those are four completely different technologies in a single package. Depending on the level of integration and the complexity of the problem, integrating dissimilar technologies isn’t necessarily a giant challenge. Today, there’s the traditional wire-bond integration. We’re seeing TSVs in simpler applications. We’re also seeing embedded chip packages where you can embed multiple die into a matrix and then connect them using more traditional chip back-end technologies. Then we see, on the horizon, this full-blown 3D chip with massive integration. The design tools are important, but I don’t think integration of dissimilar dies is the hardest part.
Maheshwary: EDA is the third problem to be solved. If you look the fabless market, the issue’s they’re looking at are whether the foundry is ready, what’s the right product, what’s the right cost? Is it cheaper to do a wire-bond design? What is the right application? IDMs do the entire chip, including packaging. They look at the cost and whether they have the yield and test issues solved. After that, it’s EDA. So EDA does need work, but we need to be extremely pragmatic about what we’re going to do. You have to use known, good die and solve problems based on them. If you’re going to do back-side routing, who’s going to do it and what’s it going to cost? Robertson: When it comes to integration, the tools aren’t going to solve the problem. Designers are integrating various pieces of IP across multiple power domains today. We validate, verify, analyze and simulate the analog vs. the digital block differently. As we go to verification of different IP across different die, there’s going to be an extension. But it’s going to be in response to what problem we’re trying to solve. Is it an integration problem, a data problem, or are we trying to do critical patch analysis across multiple die. The tools will respond, but it’s up to the customers as to which problems they want to solve first.

Tags: 3D stacking, eSilicon, Freescale, Mentor Graphics, Synopsys

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