By Ed Sperling
System-Level Design sat down with Glen Daves, director for packaging solutions development at Freescale Semiconductor; Carey Robertson, product marketing director for Calibre Design Solutions at Mentor Graphics, Rajiv Maheshwary, senior director of customer marketing at Synopsys and head of the company’s 3D initiative; Javier DeLaCruz, director of semiconductor packaging at eSilicon. What follows are excerpts of that discussion.

SLD: What are the advantages of 3D, both from a business and technology standpoint?
DeLaCruz: There are two sides of the spectrum. On one side are cell phones, where you have very limited area. On the other side there are pizza-box boards. Both of these can save on space and increase performance. But once you start going 3D your main avenue for getting the heat out disappears.
Daves: You do it because it allows you to create cool stuff. That stuff is differentiating, either from a miniaturization standpoint because you can reduce the size of the chip or the board, or from performance. Eventually there is a promise of cost savings, but that’s not the initial driver. In the emerging technology where you build the package around the chip, you’re saving on laminates. And if you have multi-chip integration, you’re saving there, too. But if you’re moving to the lunatic fringe of TSVs, cost is not the goal. It’s performance or integration.
Maheshwary: From a mass-market adoption point of view, the only limiter is cost. That’s why people do die size reduction, and it’s why people are looking at what kinds of technology can be used. ‘Via last’ is cheaper to assemble, there are much larger pitches for vias, and you can assemble these chips and get a good cost saving. Where EDA will play is in the tools around heterogeneous devices. The big driver there will be performance. Performance and power go together. There are stacked devices, or stacked devices with interposers, or side-by-side devices. What gets used depends on the application. One other dynamic is that for some of the consumer applications the desire is to get a more PCB-driven flow where the form factors are determined from the outset. It becomes an I/O optimization problem. It’s a PCB form factor driving a package pin-out driving the chip. That’s where some of our customers are trying to take us.
Robertson: There is significant appeal on the design side. We’ll truly expand what we’re doing in re-use, which gets back to the cost issue. Do designers really want to re-design their analog block that works fine at 65nm, and have to do it over again at 40nm and 28nm, when the only reason is to be able to fit on a 28nm die? It’s very painful to do that. To be able to design at the node that makes the most sense for that particular block is good for designers. Then they can use it in different applications and not have to do so much porting. But the economics have to make sense, too. There are a significant number of technical hurdles and the ROI needs to be resolved.

SLD: Where are we now in the process? There was a mention of 2D, 2.5D and 3D.
Maheshwary: There is a set of tools now moving from 2D to 2.5D. You can do stack extraction and verification working with known good dies. You may not be able to do all the floor planning and have all the capabilities for partitioning, but that’s 2.5D. When you get to the point where you can move logic from chip A to chip B, that’s truly 3D. Time will tell whether that will happen. There are lots of unknowns. Partitioning logic between chips is 3D.
Daves: There’s already horizontal integration, which has been around for 30 or 40 years, where you have two die side by side in a package. There are various forms of 3D integration for shrinking the die size. But 2.5D in the physical sense might be an interposer with horizontal die on both sides. You can imagine chip stacks growing from there.
Maheshwary: Interposers are a good example. Companies are using via-last. You have the logic through a TSV and the glass substrate. When you start putting USB on that it will be 3D, and that will happen in the next year.

SLD: When we go to 3D do we have more derivative chips or fewer?
DeLaCruz: You certainly have more opportunities for derivatives because you’re able to use the chips that already exist and you don’t have to worry about different chips with the same technologies. You already have one that works well, and you can stay at 130nm. A lot of the package-in-package and system-in-package are based on the ability to use an older chip that had a pin-out made a certain way. It’s just realigning your bond pads so it will work with the next-generation chip, even though that same chip on the inside is identical.
Daves: The promise of in-pad integration, whether or not that’s 3D, is big. Multi-die integration in package probably results in fewer silicon derivatives, but more product derivatives. You can re-use the same chip in many products.

SLD: What happens on the total cost of a chip? Does it stay the same, go up, or even go down?
DeLaCruz: If you’re able to shrink the die and use some of the older technology for a controller chip, for example, and only use the high-end of an existing chip, you shrink your cost. If you only use the advanced node for certain things, you can drop the cost. One of the difficulties, though, is there are so many flavors of integration. TSVs will drive up the initial cost. If you have examples of a newer die with an older ASIC, you have significant opportunity for cost savings.
Maheshwary: We’ve seen that. One of our customers had a set-top box with analog IP at an older technology and PHYs and a silicon interposer with the logic of the newer technology. Their cost was the same as doing a new SoC. What they expected, though, was that with the time-to-market gain it would provide huge cost savings for additional products.

SLD: Does this make node skipping easier?
Robertson: There is always a demand for new technology.
Maheshwary: The reason to move down the Moore’s Law curve if you have a 3D TSV is less and people will stay with the older nodes. There will be certain applications—processors, leading FPGAs and memory—where it makes sense to go to the next node. But it’s also very costly to get to 16nm. Stacking is an alternative. There will be a mix of customers. The mainstream will take advantage of the older nodes if this works out.
Robertson: It will be easier to move to new nodes. Some of our mixed signal customers, as they move to the newest nodes that have been pioneered by the memories and FPGAs and microprocessors, they’ve only implemented a third or a quarter of the devices those mixed signal customers want to implement. While that node may be somewhat stable, the analog guys now need to come in and qualify new inductors and three to four times the devices. They may not need that technology for the analog parts. They need that technology for the memory portions or logic portions of the design.
DeLaCruz: Something that may seem counterintuitive is that when heat builds up in 2D devices it’s a very concentrated area and it’s difficult to get the heat out. In an older node chip you have a huge technological advantage for lowering heat. In a package the best thermal conductor is the silicon. It has a huge first-order effect on how you can dissipate that heat, so using an older node as an integration layer can be a huge competitive advantage.

SLD: What happens to the software stack in a 3D chip? Does it become harder to develop?
Maheshwary: It’s a good question but we don’t know the answer.
Robertson: It’s too early to answer that. We have not done enough on the implementation side to know.

Tags: 3D stacking, eSilicon, Freescale, Mentor Graphics, Synopsys

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