By Ed Sperling
System-Level Design sat down with Ravi Varadarajan, an Atrenta fellow; Geert Rosseel, vice president of technology at Arteris; Yankin Tanurhan, vice president and general manager of Virage Logic’s processor and NVM business units, and Mike Smayling, senior vice president of product technology at Tela Innovations. What follows are excerpts of that conversation.

SLD: How real is 3D?
Smayling: 3D is clearly happening. People are building chips with 3D. As with any pioneers, they’re the ones with the arrows in their back. There are a lack of tools and a lack of infrastructure, but that will change. Applied Materials announced it is supporting the dielectric coatings for through-silicon vias. It’s important to have those tools available if you’re going to build the structures. Having the big manufacturers get involved means they see the importance of the business and the demand for multiple tools.
Varadarajan: The business need and the technical need for 3D is real. Moving to 28nm and below, there are two factors at play. One is the complexity of the interconnects. When you are dealing with 2D, the wires are incredibly long. The performance you’ll get by going to smaller geometries will be nullified by the long wires and the complexity of doing the layout. The second aspect is heterogeneous integration. There’s really no need to migrate everything you want to put onto an SoC into the new technology. That’s an impediment today. If you have an analog block and some memories that don’t need to move to the next node, you still have to do it if you’re building a chip in 2D. When you look at the complexity on one side and the parasitics on the other, both of those say you need to have some sort of 3D technology moving forward. The process enhancement has been happening and 3D technology is coming to the point where it can become mainstream. This is a wonderful opportunity where the technology is maturing and the need is prevalent. Leti, Imec and SEMATECH are all coming together. If you don’t have some sort of 3D strategy in 2012 you’re going to be left behind, at least for memory on core architectures.
Rosseel: Somebody has to take a contrary view. I think we have to define first what 3D is. You can start with a package on package, which is some version of 3D, and then you have stacked die and go all the way down to having four or five chips fully designed as an integrated circuit. I think the last one is a long way from reality, and I’m not sure if that’s even desirable. Stacked die is already happening. But implementing stacked die as multiple chips on top of each other may not be worth it. You get an extra process complexity and extra cost for doing that. There are too many problems to implement that.
Tanurhan: The real driver of 3D is that no one can pay all the costs for a certain process node. Being able to use multiple process nodes on the same application is opening that corner, and that’s how the whole mechanical 3D solution came in. For a while it was called system in package. The first time I heard the ‘3D’ word in conjunction with semiconductors design was the early 2000s, and in 2007 it started to become a marketing name. I still don’t know what it is. The IBM concept is different than an SiP. A single-die 3D is a big change, because you will get higher density, you will minimize the wiring, and you will need a lot of IP. But we are not seeing that pull yet. One of the reasons is the tools are not available and another is the yield is not there. But 3D is extremely interesting for us. With non-volatile memory the sweet spot is still 90nm and above, even though we have 65nm and 40nm available. It doesn’t make sense to take this technology to 28nm because the price tag will be enormous. The analog circuit doesn’t shrink. You have to pay more for the wafer. So stacked dies are becoming very interesting. But it’s not easy to do. The world is going to multiple processors, heavy on-chip communication and heavy processing. Now you have to cross domains from one chip to another and you cannot use the communication protocol you’ve been using. It behaves more like a PCB, but it really isn’t one. And, by the way, it’s your problem to solve the timing issues because we don’t have tools, either. For a memory block, it’s a done deal. But having multiple processors communicating on the same bus and sharing the same memory will be a heavy thing to lift for all designers.

SLD: Let’s dig into some of the problem points.
Varadarajan: You’re talking about people conceptualizing where you have 90nm, 65nm and 45nm. Just splitting the gates across the different technology nodes and figuring out the best possible layout and the routing is an interesting technology problem to solve. I don’t think we’re going to get there anytime soon. But memory is happening today. You can even extend that one step further to when you have a two-die structure and you just put in memory. You have a lot of white space on the memory die. If you look at systems on chip today, they are complex IPs put together with a bus fabric connecting them. These IPs exist in multiple technologies. You can start to question whether this IP belongs at a lower technology node or whether it can go into older technology nodes because there is empty real estate. By doing that, how do to the timing and high-speed IP look? That is a practical application. It’s memory and then also migrating entire IPs into different tiers and dies. Then you have to look at timing and your thermal profile and whether you need to do something special to dissipate the extra heat. But if you can solve all of these problems you have a viable approach.
Rosseel: We’re looking at this more from an architecture point of view. People are not going to share transistors and gates, but they are going to share IP between different die. Then the only question is how these IP blocks are going to talk to each other. We see network on chip as a communication mechanism. You need some kind of communication because they’re all developed separately and designed separately. To create that coupling you’re going to have to create some standard interfaces. They will have to be asynchronous and configurable. With standard interfaces you can test them separately and design them separately.
Tanurhan: Network on chip is on-chip. This one is off-die. There is a lot of development that needs to be done. The white space issue is real and has to be addressed, but it’s a system architect’s nightmare. It is not straightforward to have all that timing budget and model it right. The reason why it works with memory is it is very nicely encapsulated. Sharing IP blocks will require two elements. One is local management capability, so you will some type of system supervisor to make sure all that local intelligence is managed right. That is not a passive element. On the really high-speed 3D, you also will have all the cooling problems. Today you can create a really high-speed processor. If you have two of those, one sitting on top of the other, how do you keep them alive? So one challenge we have is connectivity. A second is yield. The cost function still has to make sense, too. Yield is a multiplier of cost.
Smayling: 3D has been around in ICs since 1985. At that time we were building DRAMs with planar capacitors and we couldn’t build the chips big enough because of reticular limitations so we began building in 3D structures, either trench capacitors or cup capacitors. Integrated devices like DRAMs had to start long ago, because of cost reasons, to go 3D. Cost has always driven our industry. People will do 3D or hybrids if they’re cost-effective, but they won’t be if the tools aren’t there for the masses to use them. You can always have very big engineering teams figure out ways to grind through these problems, but unless you have EDA support, ecosystem support and standards it won’t happen. How can you design a 3D chip with the tools you have? The data structures aren’t even there to understand what you’re trying to do. At TI we built these merged process devices and they were successful if you knew what you were going to merge at the beginning and then used as much of the additional process complexity across the chip as possible. If you added 5% to the wafer price but only used it on 2% of the area you had a losing proposition.

Tags: 3D, 3D stacking, Arteris, Atrenta, Tela Innovations, Virage Logic

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