By Ed Sperling
System-Level Design sat down with Ravi Varadarajan, an Atrenta fellow; Geert Rosseel, vice president of technology at Arteris; Yankin Tanurhan, vice president and general manager of Virage Logic’s processor and NVM business units, and Mike Smayling, senior vice president of product technology at Tela Innovations. What follows are excerpts of that conversation.

SLD: Why is it so important to move to 3D?
Tanurhan: The whole idea why you go to 3D is to reach volume faster. It will allow massive re-use. The only thing missing is modeling and the standards. Once you have that, you can make intelligent decisions about what to model and where to place it.
Varadarajan: A lot of that is happening today. When you look at place and route and synthesis tools today, every cell has multiple footprints—low speed, high speed, different power. There may be 25 variants of a standard-cell library. It’s the duty of the synthesis and the place and route tool to pick the right one to meet all these multi-domain objective functions. I look at 3D the same way. If I have an IP block, it might exist in two different technologies—one at 65nm and one at 90nm, and maybe one at 28nm. Each IP has different fixed footprints, timing characteristics, area characteristics and power characteristics. This prototyping tool is helping you determine whether it’s better to keep the IP at 90nm or is it better to bring it down to 28nm. What we’re doing at the transistor level has to be done at the IP level and the memory level to make this more scalable.

SLD: What happens to signal integrity if you get hot spots?
Rosseel: It’s no different than what’s happening on chips today. The only question is whether you can model the hot spots and get the heat out. There is a big temperature issue even today. With 3D, you’re going to put more power in a smaller footprint. So how do you model that? How do you know you’ve got the heat out? That is the main challenge there.

SLD: What happens to the IP and how do you test for all of this?
Tanurhan: The amount of characterization you need to do will be larger and you will need more parameters. But once you’ve added those parameters and the right modeling tools that would not be as big a challenge.

SLD: So what you’re talking about is guard-banding your IP?
Tanurhan: Yes. You need all the temperature information, and the designer or even the tool putting that information together has to make the right choices.
Smayling: I spend most of my time thinking about 1D problems. But as we scale technology to 28nm, 22nm and 16nm, the patterns are going to become very regular 1D patterns. From my viewpoint, being able to partition IP between the leading edge, which will require these kinds of design styles, while still allowing older devices with 2D design styles, is going to be a benefit for the industry. It will let us continue scaling logic functions, which are not constrained by electric fields as much as analog or some of the memories. It becomes a patterning problem, which we can deal with.

SLD: Can you find the bugs the same way in a 3D structure as in a 2D structure?
Varadarajan: You have to be able to leverage everything we do today in 2D and to build new models. New factors come into play such as mechanical and thermal stress—not just the heat—when you stack these dies on top of each other. But a lot of people who should be worrying about these problems are actually worrying about them. For this to be a viable alternative, we need to figure out how to do the testing and how to reliably manufacture it. I think it will be an evolving process over the next one or two years.

SLD: What happens to power requirements in a 3D chip? Does it go up or down?
Smayling: It will go down. You’re driving shorter loads and less loaded devices.
Tanurhan: If you are using older mature technologies your power cannot go down. It should be staying where it was. One of the tricks to re-using an older node is to get the power down. The only thing we can do is control the power more efficiently. If you do it on a single die you have to introduce a lot of trenches and you need a complex process to manage multiple voltage domains. Now you don’t have to do that. You can have die by die with different voltage domains and you can introduce a much more intelligent power structure. But it will not happen on its own. By definition the power should be going up.
Smayling: The reason it will go down is that the interconnect is dominating the power now, not the active devices. Unfortunately, we’re spending a lot of time moving capacitors.
Tanurhan: But with 3D you’ll have even more interconnects.
Smayling: But those will be shorter interconnects.
Varadarajan: You won’t have as many buffers and repeaters as on a 2D chip.
Tanurhan: But you still have to drive power from chip to chip. It’s not free.
Smayling: But it’s less than driving bonding pads and bond wires on a circuit board.
Tanurhan: Absolutely, but not always less than the wire. The whole power calculation has to be made.
Rosseel: It all depends on where you’re coming from. If you’re taking an existing design and putting it on multiple die, power will go up because you’re at capacity. If you’re taking a stacked die and putting it in a more normal 3D structure then power will go down because you won’t have to drive that much I/O capacitance.

SLD: How about multiple voltage domains?
Smayling: We’re able to separate voltage domains, which is good. That drives people crazy today. But let’s suppose I have a 3.3-volt analog chip that I’m going to attach to my 1-volt chip. I need to get that 3.3 volts out to a pad somewhere, and the PDK for my 1-volt chip doesn’t even understand 3.3 volts. It gets back to this multiple-node and multiple-domain PDK problem. That’s something we’re going to have to work out. The devices won’t even support some of these voltage requirements.
Tanurhan: Or you have to bond from the other die, which we have seen in past situations.

SLD: Let’s look at drivers for 3D. Is it cost or is it technology?
Tanurhan: Sometimes it’s IP availability. How do you get access to it? Sometimes it’s easier to get access because someone is already using it internally. It also may be the only way that architects are looking at the problem today while everyone is waiting for EDA to show up.
Rosseel: We have extended the network-on-chip protocol for a chip-to-chip interconnect, which would serve 3D because it’s very lightweight and configurable, with low latency and relatively high bandwidth. People are already using that for stacked die solutions. We haven’t seen any real 3D yet, though. Stacked die is what people are using today.
Varadarajan: Some of our big customers are seeing both. The mainstream world is not starting to think about 3D yet, but the large companies have either done it or are actively thinking about it.
Smayling: A lot of the motivation is cost, but completely new functionality is a technology driver. We think in terms of integrating multiple silicon chips. But if we can start putting optical components into the mix, now we’ve got communication bandwidth available that we didn’t have with a pure silicon solution. There’s a lot of opportunity out there that is limited by our imagination. When we start mixing these materials and properties of some of these compounds and the integration we get with analog-digital silicon, we’ll get to things we haven’t even contemplated.

Tags: Arteris, Atrenta, Tela Innovations, Virage Logic

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