Blog Review: July 7
By Ed Sperling
Mentor’s Colin Walls compares human error and the intelligence built into compilers. Everyone can have a bad day. It appears that compilers do not—unless of course the team that created them had a bad month. Another party in Conference Room B.
Cadence’s Richard Goering covers a talk by Brian Bailey that starts with an interesting premise—for all the talk about ESL and modeling, TLM 2.0 cannot be synthesized. That might explain why models aren’t being utilized at the same level in the mainstream chip design world as at advanced nodes. There’s even a video to go along with this one.
Si2’s Steve Schulz digs into who should be involved in setting standards. Answer: The guys with the biggest R&D budgets. But are they really setting standards that are best for the industry or has disaggregation made it impossible for everyone else to effectively collaborate on setting standards?
Semico’s Joanne Itow raises some interesting questions in “Decisions…” about whether foundries are taking the right approach with their processes. She even quotes Yogi Berra, one of the greatest abusers of the English language in recent history. Here’s another famous quote from the Yankee catcher: “The future ain’t what it used to be.”
Synopsys’ Janick Bergeron takes a look at automating coverage closure. He says that something that is “challenging and time-consuming” is a perfect candidate for automation. Getting there is another matter, however.
Inveterate blogger Daniel Nenni looks at the overall U.S. economy and the semiconductor economy and asks some interesting questions, mostly involving economics and jobs. It’s a big issue and there are no simple answers. It’s like trying to manage heat in a 22nm 3D IC structure. The problem is so vast, where do you start?
Cadence’s Tom Anderson looks at why UVM is ready for production use today. The big question is how many people are actually using it, though. Stats would be helpful.
Tags: Cadence, Mentor Graphics, Semico, Si2, Synopsys