GlobalFoundries Touts TSVs; Claims High-k Advantages
By David Lammers
GlobalFoundries executives said they plan to support a through-silicon via (TSV) 3D interconnect technology, with volume production expected to begin as early as 2013. And executives gave an impassioned defense of the company’s gate-first approach to high-k/metal gate (HKMG) technology, saying the gate-first HKMG flow allows a more-traditional design style and a roughly 10% die-size advantage over the gate-last process flow adopted by TSMC at the 28nm node. Both TSMC and GlobalFoundries are expected to begin 28nm production late this year with HKMG technology.
At the foundry’s day-long technology event, held in Santa Clara Wednesday, senior vice president for technology Gregg Bartlett said GlobalFoundries is currently developing a silicon interposer solution, putting an Advanced Micro Devices CPU and a DDR3 DRAM on a substrate. The interposer solution will be followed by a vertical TSV technology, which GlobalFoundries will develop with its research alliance and OSAT (outsourced assembly and test) partners. “We are not in the assembly and test business,” Bartlett said, adding that the ability to support high-volumes of TSV-enabled ICs is “a core focus of our technology roadmap. We are working with our ecosystem partners, including the EDA companies on thermal and mechanical stress simulation issues, which are very important.”
Bartlett spent much of his presentation detailing the claimed advantages of the gate-first HKMG technology, developed within the IBM-led Fishkill Alliance. Late last year, at the International Electron Devices Meeting (IEDM), several technologists said the gate-first approach is vulnerable to threshold voltage shifts in the PMOS transistors, caused by high-temperature steps following the HKMG deposition. Since then, TSMC has chosen a gate-last HKMG technology, and a war of words has ensued over which approach—gate first or gate last—is superior.
“There has been a lot of concern expressed about gate-first technology, and we’d like to set the record straight,” Bartlett told the roughly 2,500 attendees at the Global Technology Conference. With silicon dioxide-based transistors, process engineers were able to tune threshold voltages by tweaking the wells and halo implants. With the gate-first HKMG technology, Bartlett said “we have a new set of knobs to control the Vt’s on our devices. By using the knobs we now have—in how the materials are integrated in the gate stack—we have very good control on how to set the Vt’s for a range of devices. Compared to poly SiON gate stacks, we can set the Vt lower, with no Fermi pinning, and still have very stable control of the voltages.”
GlobalFoundries and TSMC executives also have differed over whether or not there is a die-size penalty to the gate-last approach. TSMC executives argue that if layout engineers are trained in the more orthogonal design style required for the gate-last HKMG approach that there is not a die-size penalty.
Bartlett said the gate-first approach allows designers to maintain the same bi-direction poly routings as the earlier oxide-based technology. It supports jogs, and allows decoupling capacitors. “Many of our customers are showing a 10% to 20% percent smaller die as a consequence of the gate-first implementation,” he said.
Linley Gwennap, publisher of The Microprocessor Report, said “if you are trying to wring out the last ounce of performance, like Intel does, then gate-last is slightly better. But for SoCs and foundry customers, gate-first appears to be a good match.”
Companies are actively evaluating both the gate-first and gate-last flows. A Texas Instruments technology manager attending the GlobalFoundries event said that TI decided not to do comparative MPW shuttle runs at TSMC and GlobalFoundries, which he said was an expensive process. Instead, TI has taken the SPICE models for each foundry’s 28nm process and run simulations to compare the performance and leakage levels. Several physical IP vendors are currently running shuttles at both GlobalFoundries and TSMC as they prepare the libraries required for 28nm designs, he added.
Joanne Itow, the foundry analyst at Semico Research, said it is unlikely that fabless IC companies will use both foundries for the same product. Instead, companies such as Qualcomm are likely to make one product at TSMC, and a different product family at GlobalFoundries. It is too expensive to port proprietary “hard” IP from one foundry to another, particularly with such different approaches to HKMG, she said. “Companies are figuring out how to match which products with which foundries at the 28nm node. It will be like Xilinx’s approach, bringing one class of FPGAs to one foundry and another family to a different foundry.”
Clark Fuhs, an analyst at CF Associates, said GlobalFoundries must convince the large fabless IC companies to give GlobalFoundries a try. “The way it has worked in the foundry space is that the large companies establish a new process with TSMC and then look for alternate sources. I’d say GlobalFoundries is on the edge right now, as they have to convince those customers to adopt the GlobalFoundries approach.”
One announced customer is STMicroelectronics. Chief technology officer Jean-Marc Chery said “up to the 45nm/40nm generation it was possible to use multiple foundry sources. It was feasible to do electrical matching and use multiple foundries. Starting at the 32nm technology, the key players are diverging, especially with the gate-first and gate last approaches.”
STMicroelectronics has created what it calls a “Fab Synch” approach, which allows it to send the same design to both GlobalFoundries and Samsung for foundry production. “This multi-wafer fab capability gives STMicro a competitive advantage,” Chery said.
GlobalFoundries CEO Doug Grose said expansion efforts are underway at GlobalFoundries sites in Dresden, Germany, Singapore, and Saratoga Springs, N.Y. He said many large companies are “nervous about the continuity of supply” if all of their foundry partners are based in Taiwan and its earthquake-prone geography. “The continuity of supply issue may be down on the list of concerns, but it there, particularly among people sitting on the boards of directors,” Grose said.
Tags: gate first, gate last, GlobalFoundries, high k/metal gate, STMicro, TSMC