What’s Broken In EDA…
By Ed Sperling
System-Level Design sat down to discuss what’s broken in EDA with Riko Radojcic, director of engineering for CDMA Technologies at Qualcomm; Surinder Dahaliwal, executive director for VLSI Core Engineering at Mindspeed Technologies; Andy Brotman, vice president of design infrastructure at GlobalFoundries, and Paul McLellan, a start-up CEO and blogger. What follows are excerpts of that conversation.
SLD: Where are the problems in chip design these days?
Brotman: We are taping out chips and getting chips out the door, but the real issue we’re see is time to volume. There’s lots of stuff that would allow us to get that fixed and ramp to volume sooner. At advanced nodes there are all sorts of new effects. We need better ways to analyze them to get to working silicon sooner. That includes all the stress effects, layout effects. How do we take layout effects into account early—maybe even estimate them.
Radojcic: We are working on the leading edge, and my sense of what’s broken is the stuff on the fringes of traditional EDA.
SLD: Where there isn’t enough volume to make it worthwhile for the big EDA companies to invest?
Radojcic: Yes. Five years ago the things on the fringes included DFM. A startup company needed to hire one or two guys to understand DFM. Now the fringes are package-chip co-design, or hardware-software co-design. They’re quite broad, fairly separate disciplines, and it’s a hard thing for startups to span and it’s not quite big enough for the big companies to feed yet. That’s where the gap is right now.
Dahaliwal: The industry has been focused on the physical side for some time with DFM and the tools that allow people to get reasonable yields and predict their yields. What they haven’t been focused on is the implementation side. When you have 100 clocks in a chip and get all those clocks synced up correctly, that brings up all sorts of new issues. I agree with the comment about co-design, as well. You may have a chip ready to go but it typically takes you another two years to develop the software. How do you bridge that gap? People have tried to do it with modeling tools, but you can’t model everything. The industry is going through an FPGA prototyping phase now. That will help drive software development ahead of silicon.
SLD: Is Qualcomm doing FPGA prototyping?
Radojcic: We do for some chips.
Dahaliwal: The FPGA gives you the test benches. Either you need a whole new testbench verification or you wing it.
SLD: Are more things broken at each new node, or is it the same stuff plus new stuff?
Radojcic: The new stuff amplifies the Band-Aid from the last node. Stress is a good example.
Brotman: Yes, it was always there but it wasn’t as significant.
Radojcic: Right, we didn’t worry about it. With 3D [stacking] we start worrying about stress in spades. It’s thinning down silicon to nothing.
Brotman: The hardware-software issues are getting bigger because things are getting so complex. And then there are physical effects that are becoming more important. They’ve always been there, but they haven’t been as important. I remember doing a study on the effect of fill at 65nm and it was negligible. At 28nm it’s not negligible.
Radojcic: That was always there, too. But what technology tends to make harder at every node has been something that a point tool could solve. What’s new is that point tools can’t solve it.
SLD: How about the big flows from Synopsys, Mentor and Cadence? How are they holding up?
Brotman: They’re adding stuff. All three of them and Magma have timing-aware fill. They force you to use a DRC (design-rule checking) tool you’re not used to using. It would be smoother with better standards and integration.
Radojcic: They are adding stuff on the leading edge of mainstream. One can argue they’re too slow. But with the fringes they’re not sure it’s going to be big enough. Synopsys has all the pieces, particularly after all the acquisitions. But I don’t see them driving this yet.
Brotman: But even with co-design, they’re talking about the need to develop models to do the co-design. Typically those are more abstract than synthesizable Verilog. On the analog side, you need models for that, too. We don’t see a whole lot of activity in connecting those models to what you’re implementing. Sometimes there’s a disconnect between your model and the analog block.
Dahaliwal: In order to do that you need all the models.
Brotman: And they need to be matched to what you’re implementing.
Dahaliwal: Exactly.
Radojcic: Which is part of the problem. Qualcomm does architectural work and hardware-software co-design two years before the technologies exist. Sitting and waiting for all the pieces—the early development stuff needs to happen two years before the technology exists.
Dahaliwal: And that’s definitely difficult for a small company.
Brotman: It’s also new for the chip developers. They have to develop models, in languages you don’t know.
Radojcic: It’s being able to do early estimating of a design to find the sweet spot for architecture and process technology before all the pieces are in place if you want to tape out at the leading edge.
SLD: The most advanced chip developers have no choice, right? That goes with the turf.
Radojcic: Yes, and in the past you could do that. A smart guru could sit down and say, ‘I know what’s going to happen at 45nm after doing a tapeout at 65nm, or 28nm after 45nm.’ You know it’s going to be smaller and leakier. When a disruptive technology like 3D comes in, you can’t extrapolate from your experience into the future.
SLD: Is it broken or just uncharted?
Radojcic: The fact that we’ve doing all of this early stuff based on a guru’s gut feeling means it’s broken. In uncharted water, that isn’t good enough anymore. So it’s broken.
McLellan: When we’ve had disruptive technologies come along in this industry, historically it’s been startup companies that produce the technology and big companies that apply them. There are almost no examples of big companies generating this stuff internally. Calibre is probably the one big exception. But startups aren’t being funded anymore. It’s not clear where this technology will come from. 3D technology is an example. There are people doing bits and pieces.
Radojcic: There are two issues here. One is that the things that are broken are too big for startups. The other is that startups aren’t funded. I think they will be. The recession is over. Startups will begin again. But the gaps are still too big for startups. Those gaps will remain even if there is funding.
Dahaliwal: What we’re also seeing is the EDA companies are focusing outside the EDA business. Synopsys is adding to its IP business. Cadence is buying Denali. How much will they invest in true EDA as opposed to leveraging adjacent markets?
McLellan: The business model for mainline EDA is broken. It used to be the case that you worked with the leading edge guys, then the mainstream would come through and that would be the cash cow. The mainstream doesn’t come through anymore.
Dahaliwal: The number of companies has gone down, too. There aren’t the companies out there to buy the tools. You’re left with a few large companies buying expensive tools and the small guys trying to live with the tools they have, taking them off maintenance.
McLellan: The small guys are doing FPGA design.
SLD: What you all seem to be agreeing on is that the business model for EDA needs to change, right?
Radojcic: We get the EDA we deserve and are willing to pay for.
SLD: But at the same time, you need EDA more than ever to solve some of these issues.
Radojcic: There’s no doubt that its scope is expanding. The EDA business model grew up when the industry was in expansion mode.
McLellan: The ideal business model for EDA is when loads of people are doing designs and lots of lots of them need tools.
SLD: How about IP? How much of a chip uses third-party IP?
Dahaliwal: In our chips it’s a very large percentage of the content. It’s external IP you build into an architecture. You wrap your own IP around it.
Radojcic: We use a lot of third-party IP, whether it’s soft, like ARM, or harder stuff, like SerDes.
Brotman: We work with the IP vendors. When we’re doing IP with a lead customer and we’re developing it with the IP vendor, there are DFM signoff models. I’ve seen IP that’s better quality and some that’s worse quality from a manufacturing standpoint. A lot of times when we’re working on the development of the IP, there are DFM criteria for them to get paid for the IP.
Tags: business, EDA, FPGA prototyping, GlobalFoundries, Mindspeed Technologies, Qualcomm