The Week In Review: Oct. 1
By Ed Sperling
Synopsys boosted the performance and team-design capabilities of its Synplify FPGA synthesis software. The new rev also adds DesignWare library IP support, which is particularly interesting for design teams that have moved from ASICs to FPGAs as markets fragment. The result of that fragmentation is less volume to justify costly ASIC development, or FPGA prototyping for those that might grow sufficiently.
Cadence, looking to partake in ARM’s growing fortunes, uncorked an optimized implementation methodology for ARM’s Cortex-A15, the processor maker’s most powerful new processor. This also fits in squarely with Cadence’s EDA360 vision of making it easier to integrate IP rather than fighting for a shrinking number of ASIC starts with traditional EDA tools.
MIPS rolled out what it is billing as the fastest fully synthesizable multicore IP, which it says delivers 2.5 times the performance of Intel’s Atom in a smaller footprint. More important might be how it stacks up against ARM’s Cortex A-15 now that the processor wars are back in full swing.
PMC-Sierra licensed a number of MIPS32 processor cores. PMC-Sierra cuts a wide swath through everything from wide-area networks to storage and fiber.
Toshiba licensed ARM’s ultra-low-power Corex-M0 processor, although the companies didn’t say what Toshiba will be doing with it. And with Toshiba’s broad line of products ranging from consumer electronics to heavy industrial equipment, we may be in the dark for some time.
Cadence also swapped CFOs, replacing Kevin Palatnik with Geoff Ribar. Palatnik came to Cadence via IBM. Ribar came from Telegent, and prior to that worked at SiRF, Matrix Semi, nVidia and AMD.
