What’s Broken In EDA…
By Ed Sperling
System-Level Design sat down to discuss what’s broken in EDA with Riko Radojcic, director of engineering for CDMA Technologies at Qualcomm; Surinder Dahaliwal, executive director for VLSI Core Engineering at Mindspeed Technologies; Andy Brotman, vice president of design infrastructure at GlobalFoundries, and Paul McLellan, a start-up CEO and blogger.
SLD: Is part of what’s broken on the organizational side of semiconductor companies?
Radojcic: It’s not so much organizational. It’s disciplines. Twenty years ago a young engineer could understand everything from beginning to end. Now, there are at least five different languages and cultures. Process guys have become material scientists. System designers have a different language. Interdisciplinary communication is very hard. That’s all the more reason why you need a structured layer to bridge that and allow co-design.
SLD: But there are different kinds of co-design. What you’re talking about involves everything from tools to architecture to all aspects of system design, right?
Radojcic: Yes. What we need is a mechanism for an architect to talk to a chip design guy to talk about, ‘If I do X, what happens in your world?’ We used to do that sitting around a table with a cup of coffee. It’s hard to do now.
SLD: Does this get harder because of disaggregation in the industry, too?
Brotman: A distributed model makes this communication more complicated. But even for a company that has most of the pieces inside, the issues are still there. I’m not sure it’s a matter of people not communicating. It’s that they don’t understand the other team’s task and how it will interact with what they’re building. If we could combine that in one place then we would solve it everywhere.
Dahaliwal: The key handoff points between architecture, system and implementation—that layer is missing. We’re trying to bridge it with these high-level models that allow you to go from C to RTL, and I don’t think it’s been proven yet.
McLellan: The attraction is the block-level of the chip. The design folks don’t acknowledge that what we’re doing today is integration, not assembling RTL all the way down to the gates. It’s mostly IP assembly. That’s also the level the software guys need to put together their platform. That level is an interesting opportunity for standardization and to be able to go up from that level or down from that level. We have bits and pieces, but you can’t hand this off to an IP assembly tool or a software development group and they take it from there.
Dahaliwal: You need constraints. How are they coming down? These are holes in the EDA approach we haven’t closed on. Coming up with the constraints is how good your chip is going to be. The EDA companies haven’t solved this yet. They’ve looked at the very high level or the very low level. They haven’t looked in between.
SLD: There are also issues such as who owns the effect of the stress on the substrate?
Dahaliwal: That’s the foundry.
SLD: But the foundry says it belongs to someone else.
Brotman: We own the modeling of those effects.
Radojcic: The integrating body, which in 3D happens to be us, owns it. We need models from the foundries. We also need models from assembly houses because they own the substrate. There is no one body. We can’t tell things like stress with a rules-based solution like we used to because now we need to ask, whose rules? When you have a distributed supply chain and an integrator like Qualcomm, we need parameters from individual players like the foundries and the assembly houses and we need an EDA solution to create a model. We are working with several EDA companies to develop a model for stress in 3D. We have to model stress tradeoffs, implications and performance.
Brotman: But in the end the foundry and the design house have the investment here. We care that you get to volume. You care that you get to volume. Otherwise we all lose.
Dahaliwal: One thing I’ve seen is that packaging is very weak. At least in a Calibre deck I have a set of rules. There is no such thing in packaging among the subcontractors. That’s a big problem with subcontractors. There is no communication between them.
Radojcic: Specifically, for them it’s not a rule-based issue. I don’t think they should gives us rules. They should give us material properties. We the users then use that to do modeling and optimization rather than trying to solve that with rules.
Dahaliwal: You still need tools to run all that.
Radojcic: Absolutely.
Dahaliwal: And you need something to check against.
SLD: Are the testing tools for built-in test effective?
Radojcic: In 3D that is blamed as one of the forces of the apocalypse.
Dahaliwal: Testing always comes last. You tape your chip out, you run scan patterns, and you find you hooked this chain up wrong. The tools aren’t broken. It’s the implementation that’s broken.
Radojcic: I don’t think there’s a gap in the fundamental technology. It’s the implementation.
Brotman: We’ve seen some instances where there are voltage integrity effects that affect how you’re running in test mode. We do have the capability to design with those effects in mind but it needs to be done and it isn’t always done because it’s too time-consuming. You’re pushing against tapeout and you miss a few problems because of time.
SLD: There seem to be broken points across all parts of design.
Brotman: There are definitely a lot of performance challenges that affect tapeout and quality. Not everything is broken.
Radojcic: If I need silicon package co-design, who’s offering that?
Brotman: Yes, that’s missing.
McLellan: If I look at that from an EDA perspective, there’s a question of, ‘Is that a big enough opportunity?’
Brotman: That’s why it’s not there.
McLellan: Yes, is there a business for creating that, whether it’s Cadence or a startup?
Brotman: There wasn’t in the past. Whether there will be in the future is unknown.
McLellan: There may not be enough return in fixing that problem.
Radojcic: All true, but it hurts there.
Dahaliwal: Why aren’t the packaging houses driving that?
Brotman: It’s the system companies that are affected.
Dahaliwal: TSMC used to drive the subcontractors to do that. They’re not doing it anymore. These subcontractors are running a very minimal business. They don’t want to invest in 3D technology.
SLD: Isn’t that the downside of a disaggregated industry?
Radojcic: Yes, and the more the integrating house has to take responsibility. Integrated fabless companies like Qualcomm have to do that.
SLD: What’s also interesting here is that what isn’t broken at one node may be broken with 3D at the next node.
Brotman: It could be.
McLellan: One of the big challenges with EDA is you can’t develop the tools until you understand the problem and have tech data. That requires designs to exist in the next technology node. You can do a certain amount of testing for 28nm doing an old 65nm design you have lying around. But 28nm designs are different. They’re not just bigger. There are things you can’t predict.
Radojcic: That’s path-finding. It’s a design flow for exploring architectural options before you do the design. But you can’t remain purely at the high level because you care about things that are physical—power and performance. It’s not an exact design. There is a gap for something like that. We worked very closely with several EDA companies to develop this path-finding flow.
