The Week In Review: Jan. 28
By Ed Sperling
Mentor Graphics won a couple of power-related deals. The Semiconductor Technology Academic Research Center (STARC)—a group of top Japanese companies that includes Fujitsu, Renesas and Panasonic—has successfully used its Tessent test methodology for low-power ICs. And Fujitsu is using Mentor’s Calibre Proprammable Electrical Rule Checker to protect against electrostatic discharge and to support multiple voltage domains.
STARC also joined forces with Cadence for a 32/28nm DFM flow.
Synopsys rolled out its DDR PHY compiler for multiple flavors of DDR2 and DDR3, complete with unlimited “what if” types of scenarios.
eSilicon has begun work on a 28nm test chip. That opens the door for mainstream chip design to step up to the next node. To put this in perspective, large IDMs have begun work at 22/20nm and 15/14nm.
Arteris won two deals. Pixelworks is using Arteris’ FlexNoC network-on-chip interconnect fabric and its memory scheduler for its video-processing SoCs. RIM, meanwhile, is using TI’s OMAP processor, which includes Arteris’ NoC technology.
On the financial front, MIPS’ Q2 revenue grew 44% year over year to $21.9 million. Net income was $6 million vs. $2.8 million last year. Even more important, license revenue increased 85%. Company executives attribute much of the growth to Android.
TSMC’s revenue rose 19.6% in Q4 of 2010, compared with the same period in 2009, but sequentially the results were down 1.9%. Net income was up 3.1% sequentially and 27.2% year over year. What’s particularly interesting is that 40nm wafers accounted for 21% of the total revenues, and 65nm accounted for another 31%. TSMC considers both to be advanced technology nodes and said this is the first time they’ve accounted for 52% of the total.
Tags: Arteris, Cadence, eSilicon, Mentor Graphics, MIPS, STARC, Synopsys, TSMC