System-Level Design sat down with Thomas Bollaert, product marketing manager for Mentor Graphics’ high-level synthesis product line; Johannes Stahl, director of marketing for system-level solutions at Synopsys; Ran Avinun, marketing group director for system design and verification at Cadence, and Brett Cline, vice president of marketing and sales at Forte Design Systems; What follows are excerpts of that conversation.

SLD: Is the TLM 2.0 model going to be sufficient? There is now software, power, IP, and new layout issues in 3D.
Avinun: I don’t think the industry needs more standards and levels of abstraction. I think the problem is actually the opposite. Between TLM 2.0 and 1.0 there are untimed models, loosely timed models, approximately timed models and cycle accurate. For each one of them the subject is not fully defined for virtual platforms and a synthesizable subset. The direction is to eliminate some of those levels and define them better. Obviously certain companies will push new levels and new standards. But if you talk with the customers the complaint isn’t about the need for new standards. It’s about minimizing the subsets and defining them better. They can’t maintain five or six levels of abstraction with five or six sources.
Cline: We agree with that. The state of the art for each level of abstraction may not be there. If you have a TLM 2.0 model that’s modeling virtual platforms at a software level that may not be synthesizable in a chip smaller than the size of a table. There are certain constraints to produce good hardware. It’s not just what you put in software. So you have the TLM model for a virtual system platform and what’s synthesizable and you might have a gray area in between. How do you migrate both so you have enough abstraction and enough detail?
Avinun: And the push from customers is to have enough source files so they can serve them for multiple use models. Otherwise it’s an infinite amount of work for them and it’s confusing. You have models here and other models here. Did they come form the same source?
Bollaert: In regards to TLM 2.0, there’s lots of noise and communication around it. I think it’s very good for what it does, which is bus-centric communications. But it’s not about using TLM 2.0 everywhere else because it’s not made for that. It’s not about TLM 2.0 everywhere. It can be complicated and it should be simplified, for sure, but it’s not going to be everywhere. What will be everywhere will be TLM 2.0 concepts.
Avinun: People are using a combination of SystemC and C++, but processor models are still based on C.
Stahl: It doesn’t really matter what’s inside the model. TLM 2.0 is an interface model. It can be a C model inside. It can be a model that generates C. It doesn’t matter.
Avinun: And sometimes people need to use TLM 1.0 and sometimes they need a certain point to move into C even before they move into RTL. The pins are still signal-level pins. If the IP you’re developing is interacting directly with the I/Os, at the end of the day you need to define the order of those I/Os, one to nine or nine to one. If you don’t, the tool doesn’t know what to do. It’s the same with RTL. I don’t see how people will be able to avoid RTL for the foreseeable future.
Stahl: If you look at model availability on a smaller scale, the customer needs models developed for simple transactors. A methodology is nice, but they don’t want to develop it themselves. They want to have a block to plug into a block diagram-based tool and start simulating. You don’t care about the simulation modeling standard. It just needs to work.

SLD: Over the next 18 months we start moving into 3D stacking, or at least 2.5D. What happens with the tools that are there now?
Avinun: As far as the functionality of the system, there won’t be any significant change. At the end of the day, it might affect the back-end tools. They might provide you a different number.
Bollaert: It’s not so much about the change. It’s another opportunity for system-level. If you can stack chips on top of each other, even simple things like memory with a through-silicon via, you can access much wider bandwidth. What are you going to do with that? Now you can completely change the architecture. You have much more bandwidth and different interconnects. Instead of accessing data that’s 32 bits by 32 bits, now you can have a much wider bandwidth. There is great potential with 3D chips.
Avinun: So if you are designing new IP and using high-level verification, you still want to make the tradeoffs. You will get the same library as today with different numbers. It will be transparent to you. And you may get different optimization. But it’s not that much different.
Stahl: But it is more design space. The technology we have today provides a huge space for design exploration. Maybe this will add another dimension. But it’s not fundamentally changing the equation.
Bollaert. It does provide a wider opportunity for ESL. But it’s more than that. There will be a change in technology, as well. It’s not just about libraries. Libraries will change and they will reflect some new possibilities. But you also need to be aware of placement. If you have TSVs and I/O clamps in your chip you cannot just assume your design will work. 3D adds a new dimension.
Cline: It’s trickle up technology. As soon as people get good at 3D this information will move up. You only automate and abstract something once you become expert at the root level. Over time we’ll get really good, the models will get really good, the understanding of what to do with those models will get really good, and then people will start to use those better.
Avinun: There is a challenge to link ESL to high-level synthesis and the place-and-route tools. That’s the first-order challenge. But whether it’s 2D or 3D, first we need to solve the initial challenge.Back in 2005 when people talked about the challenges in ESL, one was the specific implementation capabilities of RTL. We’ve gotten better at this, but even today many tasks are being done at the RTL level rather than earlier. We have to solve this problem before we move to 3D.
Stahl: Someone needs to simulate at this low level. Once you can simulate you can model, and then you can have a synthesis flow to utilize this information.
Bollaert: Modeling and simulation cannot go hand in hand.

SLD: From an education standpoint this is a different world, isn’t it? Right now most ESL is for top customers. In the future everyone will have a role in complex designs, and everyone can use these tools.
Avinun: But if you look at the key challenges, it’s still the integration of IP and of hardware and software. If something hangs up you need to look back and figure out if it’s the IP you bought or one of the software stack layers. Those problems are still going to be there.
Cline: A big company is a subset of the market. You have early adopters at these companies, but if you go to the designer next door they may not touch it. Then you can go find a startup that’s going to bank their future on a new methodology because it’s quicker. Any company can be a subset or superset of the market. I’m not sure it changes our education mechanism.
Avinun: We all have the challenge to educate designers. That’s half of our engagement process, especially for the new tools. But every time you go to the next group it seems they don’t know anything about this and you have to start all over again. The industry has been stuck at the same level of abstraction for 20 years. The people who were out of college 20 years ago don’t want to learn about something totally new. And if you talk to the recent college graduates they may know software but not hardware. You have gaps on both sides. Over time it’s changing, but it’s changing slower than you want.
Cline: There’s about $200 million in ESL revenue. We don’t think that’s the goal. There’s $2 billion or more. As a result all the companies here are pitching a common message. That hasn’t happened in all segments of EDA, but it is happening in ESL.
Bollaert: Today HLS can do more than blocks. It can do complete subsystems. There are a lot of benefits for people out there. Whether they want to test hardware and software ahead of time, validate architectures for performance or power, or reduce time to verified RTL, ESL can really help them.
Avinun: Once we get to the point where people can’t compete without these tools, then you’ll see a major shift in the market. I think we’re getting close to being there. Large companies—at least their executives—are realizing this is the case. They’re instructing their middle management that this is the way you need to structure the company to do this. It takes years for these shifts to occur, but once they do start the shifts happen very fast.

Tags: Cadence, ESL, Forte Design Systems, Mentor Graphics, Synopsys

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