Blog Review: March 9
By Ed Sperling
What’s in a name? Apparently not enough. Cadence’s Tom Anderson looks at some alternative suggestions for DVCon.
Mentor’s Thomas Bollaert cites some really interesting verification stats, which were presented at DVCon by Mentor CEO Wally Rhines.
Synopsys’ David Hsu examines high performance computing in a cloud and what effect that could have on EDA. The impact on chipmakers’ operating expenses could be significant, but only if they’re actually willing to move data into the cloud.
Harry Gries, aka The ASIC Guy, talks about the blurred lines between winners and losers in sports and in EDA. In EDA there’s certainly good reason for being civil to the competition, though. You never know who’s going to be your next hire or your next boss.
John Cooley’s DeepChip features an anonymous but positive report of a speech by VC Jim Hogan on SoCs, IP, design management and verification. In Hogan’s opinion, the future is all about SoCs and IP.  DeepChip also ran the results of a Mentor survey on high-level synthesis from Shawn McCloud. What’s particularly interesting are the advantages for cycle-accurate implementations of control logic using HLS and the split between untimed, partially timed and cycle accurate on algorithm implementation.
Cadence’s Richard Goering drills down on the Open SystemC Initiative with a video interview of its chairman—Intel’s Eric Lish. Goering asks all the important questions.
Mentor’s Mike Jensen compares fast cars to simulation. That assumes, of course, your simulation actually runs fast.
Synopsys’ Navraj Nandra looks at a new standard, G.hn., which unifies the physical layer and data link layer over multiple wire types in the home. The next step is unifying wired and wireless, which should have interesting ramifications for all sorts of consumer and business electronics.
Speaking of converged communications, Semico’s Tony Massimini takes the covers off Thunderbolt, the new and much faster interconnect technology developed by Intel that made its debut in Apple’s new MacBook Pros. The big question is how fast it will be adopted—and by whom.
Cadence’s Joe Hupcey rolls out another video, this one for assertion-based verification involving a paper from Freescale and Cadence. Considering formal verification’s continued growth, this is an area that everyone will need to get comfortable with.
Mentor’s Dave Rich offers up some inside knowledge for using UVM 1.0 with Questa. If you work in this environment, this stuff should come in handy.
Also deep in the weeds of verification, check out the blog by Verilabs’ Asif Jafri in Synopsys’ VMM Central.
And on a broader note, Cadence’s Sharon Rosenberg looks at TLM 2.0, UVM 1.0 and what they mean to verification. At 28nm, quite a bit.
Tags: Apple, Cadence, Freescale, Intel, Mentor Graphics, Semico, Synopsys