System-Level Design sat down to talk about what makes a company successful in the IP market with John Koeter, vice president of marketing for IP and systems at Synopsys; Art Swift, vice president of marketing and business development at MIPS Technologies; Vishal Kapoor, vice president of product management for SoC realization at Cadence; and Charlie Cheng, CEO of Kilopass. What follows are excerpts of that discussion.

SLD: What happens to IP when we move into 3D stacking?
Koeter: The answer depends on whether it changes the chip architecture. What we’re seeing now is it isn’t changing the architecture. What most people are doing is taking an active processor and stacking DRAM on top of it. That’s not changing the fundamental way they’ve chosen to partition their chip. So that hasn’t changed our business yet. But being the leader in interfaces, clearly we’re looking at that all the time. There’s a camp in the mobile area that’s pushing wide I/O for DRAM, which is enabled by 3D packaging.
Kapoor: When you get into the implementation you have to worry about that. I agree that concept has been around for awhile. When you start thinking about the differences in geometries, any time you change geometries you have to take physical effects into consideration.
Cheng: I disagree. We license to three out of the top five DRAM companies. DRAM is a prime candidate for stacking. Somewhere in the stack there’s a dedicated chip that does repair. When there’s a repair it keeps adding to the defect map. From wider bus to the way a stack is managed, there will be a lot of changes in the architecture and requirements. Where there is a problem there will be a solution. The question is whether it will be differentiated enough so that you can go to a customer and get paid for that.
Koeter: There’s potential that isn’t being actualized right now. If there was a fundamental change in the architecture that would be a problem. If there was a fundamental difference in the partitioning with the digital function being at 28nm or 22nm and there is a 130nm chip with analog that would be a challenge, too, but we’re not seeing that right now.
Cheng: It’s not going to happen in 2012 because there are some problems that haven’t been solved yet. When consumers see some great results from stacking is when you’ll see a shift.
Swift: If our customers are putting 200 cores, sometimes homogeneous and sometimes heterogeneous, on a chip, that gets magnified with a 3D approach. That will have to impact the business of EDA tools.
Kapoor: That’s true, but the question wasn’t around EDA tooling. From an EDA perspective that will certainly be the case.

SLD: Are the processors cores going to be split up across chips, or will they all be in one place?
Swift: In a heterogeneous environment there could be lots of different processors doing different things. You might have a cluster of processors doing the data processing, but you can still have lots of ancillary processors. They won’t be necessarily be clustered together. Analog functions will be clustered, as well.
Koeter: The processor, the interconnects and the DRAM interfaces are usually—but not always—the determining factors in the performance of the chip. Will the processor and the interconnects move off chip? I don’t see that happening. Could the DRAM interface change to a very wide interface? I can absolutely see that happening through the apps processor and memory.

SLD: That’s a through-silicon via approach?
Koeter: Yes.

SLD: There is a wide variety of IP in use, and some of it is still developed internally by chipmakers. Where is it toughest for IP vendors to break into the homegrown IP market?
Cheng: There are two areas that are hard to outsource. One is tied to the process technology itself. The recipe is hard to get, so it’s hard to complement. It’s also not very profitable for outside companies because you have to customize for every process technology. The second area is IP that has a lot of proprietary applications, such as a proprietary audio transceiver that is different from Bluetooth, using radio waves and CD-quality. You couldn’t license that widely because the greater industry requires compatibility. To the one or two companies that really need it, they’re better off doing it themselves.
Kapoor: And that isn’t IP anymore. By the classical definition it’s still intellectual property but it wouldn’t translate into a merchant IP model.
Cheng: That’s correct. The second one is where the highest monetary value is. The MIPS S-1 registration document is a great example. It got $5 for every game console sold and $2 for every cartridge sold for the Nintendo graphics engine. Each one of us would kill to license IP where the customers pay us that amount of money.
Koeter: There’s a different level of maturity in outsourcing depending on the function. Microprocessors are the most widely outsourced. Interfaces are the next most common. And in our business we’re seeing 17 of the top 20 semiconductor companies in the world outsourcing interfaces to us. Memory is increasingly outsourced, as well. But when you look at analog IP, RF and security—those things are not being outsourced. They’re much earlier in the outsourcing phase.
Kapoor: If you go back to processors, interfaces, and memory and storage being the three big broad areas of oursourcing, outside of that it’s highly specialized. If I want a PLL I’m going to have to go to a services house. They may have some repeatable processes internally, but it’s custom-built for me. There are also things that will differentiate my chip. That’s my secret sauce. But the model will go to more and more outsourcing and standards-based stuff because the value is in the software.

Tags: 3D stacking, Cadence, IP, Kilopass, MIPS Technologies, Synopsys

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