Blog Review: April 20
By Ed Sperling
Cadence’s Qi Wang looks at the biggest headache in power management at advanced nodes—how to turn things off. This isn’t always as simple as it sounds.
When Aston Martin introduced the big red “start” button it was supposed to be cool—a street-legal version of what’s been used inside racing cars for years. Mentor’s Mike Jensen just encountered one on his rented Nissan Altima rental. What’s next? A blue button? Whatever you do, don’t hit the yellow button.
Si2’s Steve Schulz looks at the EDA360 concept and asks an interesting question: “If not EDA360, then what?” So far there don’t seem to be any other takers.
Synopsys’ Hezi Saar digs into TSMC’s new process for mobile and what it means for the larger chip market. This is an interesting business perspective with roots deep in the technology.
Cadence’s John Pierce pulls together some references for improving the final integration of analog IP. This stuff is going to be particularly important in 2.5D and 3D stacked die.
Mentor’s Colin Walls looks at the criteria for choosing an embedded OS. Given the possibility for saving a significant amount of power, this is an important consideration.
Cadence’s Richard Goering reports on an IEEE workshop that identified requirements for stacked die adoption. One of the keys to making this all work: Enthusiasm. Given the challenges of developing 22nm analog IP, there aren’t a whole lot of other choices.
Mentor’s Harry Foster rolls out part six of his epic on functional verification based on an independent study. There’s more to come, too. This is either going to turn into a book or a miniseries.
Speaking of books, Synopsys’ Karen Bartleson just produced a book based on tweets about standards. Given the size of tweets, you can power through this book at stoplights.
Deepchip’s John Cooley has published a response to an irate Denali memory model customer about what the Cadence acquisition means for future support. Apparently Denali products will be supported for at least four years. Case closed.
Synopsys’ Eric Huang says that fully integrated USB 3.0 in chipsets is a done deal and will start showing up next year. As he rightly points out, that means no at no cost to the consumer.
Cadence’s Srikanth Vijayaraghavan questions whether some evolving language standards will address mixed-signal verification. The fact that anyone is even dealing with this subject is a step in the right direction.
And in case you missed the latest issue of the Low-Power Engineering newsletter, here are some blogs of note:
–Synopsys’ Cary Chin examines the fine print on contracts for using iPhones as a hot spot.
–Mentor’s Barry Pangrle looks at the cost of simulation vs. emulation from a power standpoint.
–Apache’s Aveek Sarkar digs into power budgets and why there’s a growing imbalance.
–And Mimasic’s Bhanu Kapoor overlays the ITRS roadmap on IC design. The results are…well…hot.
Tags: Apache Design Solutions, Cadence, Mentor Graphics, Mimasic, Si2, Synopsys