Big Three Focus On Software And Power
By Ed Sperling
While the Big Three EDA vendors still compete in traditional EDA such as layout, timing and verification, they are expanding far and wide into software and low power.
EDA360, take two
Cadence rolled out phase two of its EDA 360 strategy, adding new tools that the company claims will reduce system integration time by up to 50%.
“Applications are at the core of all successful devices,” said John Bruggeman, chief marketing officer at Cadence, following up the story the company began unfolding a year ago. “This is no longer about form, size and weight. Applications cause winners an losers.”
He noted that Cadence expected complexity and economics to slow down new SoC development after 40nm, but the reverse has actually happened. In fact, the proliferation of devices also has had a ripple effect on infrastructure, the smart grid and even out into the green effort.
Cadence’s rollout includes its Rapid Prototyping Platform and its Virtual System Platform, which have been integrated with its Palladium emulation and Incisive verification platform. The aim is to develop hardware and software in unison and to be able to verify it much more quickly. The Virtual System Platform will be used to debug hardware, software, memories and registers, which the company says will enable “system analysis and rapid handshake” between the hardware and software teams.
Gary Smith, of Gary Smith EDA, said the concept is interesting. He said the real proof is in market acceptance of the approach over time. Still, there seems to be at least some initial interest. Kevin McDermott, director of market development for ARM’s system design division, said the ability to design the application, middleware and hardware in sequence is critical because it allows the application to become the driver, with the middleware and hardware optimized for the application and then verified altogether.
Embedded analysis
Mentor Graphics took a deep dive into embedded software, which has become a particularly thorny issue for many hardware developers over the past couple of process nodes.
With chipmakers now responsible for delivering an increasing part of the software stack—drivers, middleware and embedded software—the challenge has been finding tools that are valuable to software engineers but which also are aware of the hardware changes.
Mentor bought pieces of CodeSourcery in December for its toolchain products. The rollout of the Embedded Sourcery CodeBench is the first major release following that acquisition. The CodeBench suite is based on Eclipse, the Eclipse C/C++ tools and compilers, and a GNU toolchain, which is used to build and debug embedded applications.
“The old approach to this problem was printf,” said Brad Dixon, product manager for Mentor’s Open Source Division. “That’s unmanageable in advanced SoCs. With our System Analyzer you can see and analyze system data. What we got from the EDA side is the ability to manage large quantities of data.”
He noted that Mentor is looking at adding power data into the mix in the future, as well, but declined to comment further.
Low-power manufacturing process
Synopsys, meanwhile, teamed up with Shanghai Hua Hong NEC (HHNEC), one of the large foundry providers in China, to create version 3.0 of its 130nm low-power reference flow, which now includes the Synopsys Eclypse Low Power Solution as well as Formality for low-power equivalence checking, MVRC for static rule checking, Power Compiler for power optimization and multivoltage simulation using VCS.
This development is particularly important in the Chinese domestic market, as well as developing economies, where price sensitivity is extremely high and low power is considered a critical component of cost of ownership.
Tags: Cadence, Mentor Graphics, Synopsys