By Ed Sperling
System-Level Design sat down to discuss 2.5D stacked die with Vassilios Gerousis, senior architect at Cadence; Drew Wingard, CTO at Sonics; Kurt Shuler, director of marketing at Arteris; Kalar Rajendiran, senior director of marketing at eSilicon, and Hamid Savoj, technology fellow at Magma. What follow are excerpts of that discussion.

SLD: Is the push to 2.5D stacking really a simple evolution, or is this transition going to be more difficult than we realize?
Gerousis: There are few things we have not tried before. The silicon interposer is not just another interconnect. Another issue is RC extraction. There is no diffusion, which means there is no ground. We don’t know how to calculate the RC values. What is the reference point? Those are challenges we haven’t dealt with.
Shuler: Most of our customers are looking out at 3D logic and memory. We really haven’t seen too many questions surrounding 2.5D interposers. In 3D there are a lot of questions about the interconnects and how you can communicate through many pins and connections.
Wingard: I looked at one of our customer’s design recently. It’s an eight-layer stack, with lots of memories, and one of the layers is an interposer layer. It’s there because the through-silicon via technology isn’t ready for real high-volume production. One of the uses of the interposer is as a redistribution layer so they can get bond wires into those things in the middle. In some stacks where people were using spacers they will start using interposers instead. That solves a real practical problem. It’s real, it’s here, and it’s being driven by form factor more than performance.
Savoj: We have a few customers doing real 3D. We have taped out many chips. There is interest in 2.5D, but there is a lot of activity already in 3D. These are memory-based.
Rajendiran: 2.5D is here and real. There is a business need driving it, too. A few years ago everybody created IP blocks, which worked fine at the older technology nodes. Right now you have a lot of IP, but it’s in existing chips. Meanwhile, the risk has been going up for custom-design chips so that if you make a mistake it’s now a multimillion dollar mistake. This is a perfect storm, and 2.5D is a nice intermediate step to solve this. Maybe your SerDes is at 90nm and your ARM processor is at 28nm. But you can put them all together and get them out in a reasonable amount of time and not have to spend too much time on verification. In the past, the compelling business-risk ratio for this kind of thing wasn’t there. It is there now.

SLD: Was the delay in getting to stacking of die cost or technology?
Wingard: The delays in getting to 3D are substantial and well-documented. One of the challenges is the lack of standards. The idea that you’re going to layer one thing on another requires standards. You need to know the size of the connections, the verticals of the connections and how thin the wafers can be. But 2.5D doesn’t have any of that. It’s the mental equivalent of a PCB.

SLD: Xilinx already is touting 2.5D. What’s different about that?
Wingard: Theirs is less focused on form factor and more on scalability. But that’s what makes 2.5D so practical now. The work that the flash industry did on proving how to stack and do these intermediate wire bonds in massive volumes at low cost means that changing that layer for interposers is pretty minor. There are some characterization problems that require you to figure out what you’re going to build before you actually build it. But compared to making 3D work, this is much easier and very practical.
Rajendiran: The interposer is closing the gap between what you can do on a chip and a PCB. 2.5D is an easy solution.
Gerousis: Some of our customers are using 2.5D for high-performance processors. You have a lot of wattage, and that creates heat. And you want to link it to a memory. It becomes a practical environment for high heat and high wattage. 2.5D is a better environment than package on package. The other thing associated with it is that 2.5D affects performance of devices. If you put the TSV in a silicon chip, you’re not interacting with other active devices. You can connect to the package through a silicon interposer.
Wingard: The thermal benefits of using silicon as your interposer are really well known. Not only do we get the scale benefits, where the interposer can be closer to what we do on regular high-volume IC manufacturing these days, but we also get the thermal benefits. Even if we stack these on top of each other, the interposer in the middle has the same expansion coefficient as the die on each side. So it becomes a much more reliable package, as well. There are real benefits thermally, as well. These interposers help pull heat off the high-power application processor.
Shuler: Do customers have enough information to make a decision about whether to use a standard PoP and the cost ramifications of using 2.5D?
Rajendiran: That’s one of the things value-chain producers do. We’re part consultancy. We’ve built up a knowledge base over the past 10 years. It doesn’t make sense all the time, and we have the cost details to be able to make the decision of when it does or doesn’t make sense. If you have a regular structure chip, it may make sense to break it into tiles because yield improves. It varies, but not all customers would understand that. Big customers have so many chips that they’ve done with standard methodologies that it makes it easier. For smaller companies, one chip may have been done by one guy while another was done by somebody else.

SLD: Are the tools there?
Savoj: The biggest problem today is dividing system-level design into layers. How do you partition? What model goes where? If you’re stacking them, how are you going to distribute power? Which one is going to have more power? You’re going to have more heat in there. All of these things are new. We haven’t done them in the past. And the floor planning side is going to be very challenging.
Wingard: That’s doing real system-level design with flexible boundaries between the layers in a stack. But what we’re seeing mostly right now is a small amount of custom design and lots of re-use standard logic or previous-generation chips. For that class of design we’re in pretty good shape. The electrical environment in a 2.5D chip is way better than package on package. Thermally we’ve got lower-induction connections. There are lots of things that are much better. But there are all the materials handling challenges. This is a whole different kind of deal where you ship known good die. We need to think about the business relationships, too.
Gerousis: There are enhancements you need to do to the tools, but if you can enable some interactions between chips so the footprint on the top matches the footprint on the bottom of the chip.

Tags: 2.5D stacking, 3D stacking, Arteris, Cadence, eSilicon, Magma, package-on-package, Sonics

This entry was posted on Thursday, June 30th, 2011 at 12:01 am and is filed under Round Tables. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.