Battle Brews Over Test
By Ed Sperling
After years of slogging along the test market suddenly has exploded, attracting new investment, new interest—and inviting plenty of confusion.
There are several good reasons for this buzz around test. First, the sheer size of chips and the number of components being put on those chips is enormous. Being able to get them out the door in working order is a monumental feat, and test is a critical piece in that equation.
Second, the amount of third-party IP and software that needs to be integrated into these chips is growing. Not all of this technology is adequately tested by the vendors, and in some cases chipmakers don’t even know the actual source of the IP that is on their chips. That makes testing the chips thoroughly far more important.
And finally, test is a way of reducing low yields. At 180nm that might not be such a big problem, but at 28nm or in stacked die it can cost a bundle. In addition, it can delay the introduction of a chip, which can cost many more millions of dollars.
That has led to a massive effort to test at all levels in a flow. But it also has led to widespread confusion about how early to start, where to start, and how many levels of testing are actually needed. The Big Three EDA vendors, building on their integrated flows, have added test in at all levels, and all are claiming big improvements in efficiency. But in a customer environment with multiple vendors’ tools, as well as homegrown tools, the gains are a bit murkier.
Put in perspective though, choice is typically good in the long run, and there certainly is no shortage of tools to choose from. Mentor Graphics, Cadence and Synopsys all rolled out new tools or enhancements to their lineups this week, in conjunction with the International Test Conference.
Mentor Graphics added user-defined fault models and cell-aware automatic test pattern generator (ATPG) to its Tessent line, which is particularly important in the DFM sector. The company says the changes allow chipmakers to spot faults without having to wait for fault model libraries to catch up. Mentor also took the covers off a joint development effort with ARM for a comprehensive test methodology for ARM-based designs, which automates memory test and repair.
Synopsys, meanwhile, has been heavily leveraging the test portion of its Virage Logic acquisition last year. It rolled out enhancements to its TetraMax ATPG and Yield Explorer lines to help identify and zero in on physical defects more quickly, and expanded the built-in self test (BiST) portion of its memory testing. One of the big problems in SoC test is that once an error shows up, it’s difficult to pinpoint quickly because of the huge number of components. Even single blocks are large and complex.
To make this work effectively, test needs to be built into the design much earlier—in some cases, such as BiST, at the architectural phase because it actually needs to be included in the floor-planning stage. “We’ve found that design impacts test, but test impacts design, too,” said Robert Ruiz, Synopsys’ senior product marketing manager for test automation products. “What we’re seeing now is the intersection of power and test.”
And Cadence has been banging the drum for design for test, logic BiST and low-pin-count compression architecture scanning for mixed signal designs.
Around the fringes of these there are also lots of point tools, a market that becomes increasingly confusing as the manufacturing rules, software, physical effects and various levels of the design flow get compressed at advanced nodes and ultimately in stacked die. As with most rapidly growing markets, expect more confusion before there is order.
Tags: Cadence, Mentor Graphics, Synopsys, test