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Comprehensive UVM/OVM Acceleration

Today’s traditional design flow involves design at multiple levels of abstraction. As the design implementation is refined and the verification vehicle changes, the testbench needs to adjust to abstractions from transaction-level simulation, and RTL simulation to hardware acceleration. But the challenge is that separate verification components, testbenches, tests, and plans are developed by separate teams at different abstraction levels. This requires more expertise to learn and understand, more code to develop and maintain, and larger teams to fund and manage.

This white paper describes a consistent and comprehensive Universal Verification Methodology (UVM)/ Open Verification Methodology (OVM) that prescribes substantial reuse across multiple levels of abstraction and facilitates a metric-driven verification (MDV) flow. While this document focuses on UVM/OVM acceleration, it also touches on other abstraction levels, such as transaction-level modeling (TLM).

To download this paper, click here.

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