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System Dictates Transistor Design

By John Blyler
It is easy to miss the connection between advances in transistor architectures and the relationship to the larger system. How do improvements in transistor development fit into the big picture?

This is not an esoteric question, since improved transistor designs are essential to meet ongoing system-level demands for lower power, higher performance, small size, and reduced cost. Higher level system constraints influence what transistor improvements will be pursued.

A major driver of today’s systems is the emergence of a tightly connected electronic ecosystem consisting of an infrastructure core (data centers), smart mobile devices and sensor networks. All three components share the common requirements for high-speed electronics, increased battery life, greater data storage, multi-functionality, reduced cost and ever shrinking form factor.

Each of these affect the trade-offs  with different set of needs. For example, the data centers in the infrastrure core require the highest performance with efficient power usage. Mobile device require high performance with even greater emphasis on power usage.  Sensors require lesser performance but ultra-low power, even relying on engergy scavenging techniques.

The foundation for all of these system applications is the transistor. The challenge is that this most basic of hardware building blocks must meet all these different needs at different levels. To date, this challenge has been met by feature size scaling, which is a result of Moore’s law. Continuous scaling of transistors has provided the necessary improvements in performance while reducing power consumption, cost and die size.

But in the future, mere device scaling techniques will not be enough. Scaling on the material side will also be required at the sub-10nm nodes, to continue to meet performance, power, area and cost requirements. Even today, chip designs are transitioning from planar to FinFET transistors. There will also be continuous work to enhance the transport of devices via high-mobility, non-Silicon channel materials. Finally, memory cores are evolving from 2D to 3D structures.

“Scaling must be done at many levels,” explained An Steegen, Imec logic director at the recent Imec Technology Forum (ITF) in Lueven, Beligium. Comprehensive scaling will be needed on the transistor, process and – equally important – system side, through the use of 3D interconnects, she noted. New interconnect schemes will enable scaling at a higher resolution at the die-level.

Since the 1990’s, lithography enabled scaling has help maintain Moore’s law with a continuous push of transistor feature size scaling. Lithography improvement have permitted tighter poly pitches and increased gate density. But an inflection point occurs at 90nm, which lead to the need for material scaling.

According to Steegen, lithographic methods had to be complemented by material-level scaling beyond 90nm. Material scaling led to the introduction of High-K Metal Gate (HKMG) processes and fully depleted devices. At 22 and 14nm nodes, non-planar devices will be required to manufacture the thin channels with improved electrostatics will be needed to allow the transistors to operate at much lower supply voltage (lower power) while still providing adequate performance.

What lies ahead for both feature and material scaling? Imec’s roadmap provides one perspective (see Figure 2). Beyond 14nm, band engineering will be required to enhance transport or the mobility of the transistor through the use of Group IV type materials. These materials will complement the enhanced electrostatics for the device through band engineering.

Much uncertainty lies beyond 14nm. Undoubtedly, new transports will be introduced to fully evolve the capabilities of transistors. Some of these new transports will include tunneling FETs. The tunnel field-effect transistors (TFETs) are seen as successors to today’s metal-oxide-semiconductor (MOS) FETs due to their extremely low voltage requirements.

Another possible innovation beyond 14nm might be extreme channel electrostatics, explained Steegen. Such extreme channel confinement goes one step beyond Fin-Fets into nanowires. Quantum characteristic are another possible improvement, where traditional charge-based technologies are replaced with electron spin devices.

While the transistor remains the elemental building block for all semiconductor electronics, traditional feature scaling techniques will not be enough to meet future needs. That is why transistor designs must be seen in the context of the whole circuit and even larger electronic system (data center, mobile devices and sensor networks). This is clearly the approached used at major research and development operation such as Imec.

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