By Ed Sperling
System-Level Design sat down to discuss the future of stacked die with Riko Radojcic, director of engineering at Qualcomm; Prasad Subramaniam, vice president of design technology at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta; and Herb Reiter, 3D/TSV working group chair for the GSA. What follows are excerpts of that conversation

SLD: Aren’t there physical effects that need to be dealt with by the standards groups, as well?
Radojcic: No, the focus for phase one is to drive standards exchange mechanisms within the supply chain. What does a carrier look like and how does the foundry ship a thin wafer to an assembly house and what does the handler need to have? What is the inspection criteria? There is a set of standards in the manufacturing flow intended to link the chains within the supply chain rather than standardizing inside a link. There isn’t much focus on a standard TSV. It’s how you ship 10 wafers.
Subramaniam: There’s also the issue of who owns the library for the wafer. Now that one company is doing part of the processing and another company is doing part of the processing, who owns the problem if there is an issue with the wafer? That’s an issue that has not been resolved, in my opinion.

SLD: The business issues are interesting in 3D, particularly if you have known good die creating a bad die.
Radojcic: Yes, we totally agree. But before we get too pessimistic about this, the world is shipping billions of PoP parts and there is a perfectly good PoP business model.
Subramaniam: It isn’t that it can’t be worked out. But it still has to be done.
Radojcic: And it could be an opportunity for companies like eSilicon to take responsibility on both sides.
Reiter: Test will be a big issue, too, especially if you have logic chips on top of each other. But this will be two or three years away. One logic layer with a memory stack on top of it is probably manageable.
Gianfagna: Known good die backs up to test, too. We grew up knowing about process monitors and paddle transistors and wafer acceptance tests and probe and package assembly. What else do you need for exchanging slices? Don’t you need more acceptance tests?
Reiter: The test guys are finally interested. People are coming forward to learn about 3D because they realize you can do a lot with built-in self-test and minimize the time of the tester.
Subramaniam: If you look at how we package parts today, we test them on the wafer. We don’t package parts blindly by taking parts and putting them on the package. How is it different? You still have to test something on a die before you go to the next level of assembly. The issue is that with 3D IC you won’t have all the pins accessible.
Reiter: And you can’t use PoP cards anymore.
Subramaniam: Yes, and that’s why I believe we’re heading in the direction of BiST. That enables you to test the die in a 3D environment.
Gianfagna: That backs up into an IP opportunity and a design challenge to make all that work. The business issues can be solved with some technology issues.
Radojcic: A lot of us have questioned how we test logic on logic, or memory on logic. But if you look at Wide I/O, it’s going to be shipped in a package that’s going to be tested like any other package. The only thing that won’t be tested are the microbumps and the drivers that go with it. Otherwise, the coverage is the same. It’s shipped not as a die but as a package unit. You test logic the same way you always did. So when you stack it, you have untested TSVs. That’s an incremental risk. But that shouldn’t be too bad. There’s also a potential loss of memory die due to the assembly process. That shouldn’t be prohibitive, either. But for early implementation, memory and logic shouldn’t be too bad. The hard part will be 2.5D. How are you going to test the interposer? It’s only wires, and it’s yield is not that good. So you have to take perfectly good die and put them with an untested interposer. That’s the test challenge. The only way to test an interposer is microcoding. But the things most of us spend 90% of our DFT time worrying about aren’t so bad.
Subramaniam: I don’t think it’s that simple. How do you handle temperature test? Generally when you package a product you test it at different temperatures, not just room temperature. But wafer test is only done at room temperature. Now you have good die that are tested only at room temperature, you’re putting them on a 3D package, and you don’t have the ability to test the assembled solution at different temperatures.
Radojcic: There’s nothing to stop you from doing post-assembly testing.
Subramaniam: You need to have all the pins of the die. If you have two die connected internally, you may not have access to those pins externally.
Radojcic: I’m assuming, perhaps foolishly, that whoever has built this thing has designed a scan solution of some kind.
Subramaniam: That may not always be possible.
Radojcic: If you have designed your system so that it is intrinsically untestable, you get everything you deserve.
Subramaniam: That’s why a BiST solution is appropriate. Scan may not do the job.
Radojcic: You have to do a good DFT job. It’s no different than for a 2D SoC. You have to provide the infrastructure to have observability and testability. Whether it’s 2D or 3D doesn’t make any difference.
Subramaniam: But the number of pins you have in 3D that go to the outside will be far fewer. Observability with the outside world is limited.

SLD: Does it become harder to do these tests if you are working with multiple power domains and portions of the chip being turned on and off all the time?
Gianfagna: There’s more opportunity for power domain definitions in a 3D stack than in 2D.
Subramaniam: I don’t see it as being any different.
Gianfagna: The problem gets bigger, but it’s the same problem. There is a related issue of proximity effects, though. Test over temperature gets interesting. How a system will behave over temperature is not obvious. In a 2D chip it’s more obvious.

SLD: Strangely, it may run faster, right?
Gianfagna: Yes, that’s true.
Subramaniam: This is where the analysis tools come into play. You need to model the whole problem.
Gianfagna: Nothing is new here, but it’s a bigger, more complex problem with more interrelationships. The tools will probably break due to capacity.
Radojcic: This is another tool issue or flow issue. Today most of us look at timing where everything is hot or everything is cold. You don’t have to deal with gradients. In 2D you deal with this by doing a good job of characterizing a product. Die A can be perfectly fine. Die B can be perfectly fine. But when you slap them together you may have a gradient that is different and you can’t characterize them separately. You need the ability to have timing characterization based upon thermal gradients, and there is no tool that does that today.

SLD: Don’t we also need to add even finer-grained capabilities into tools? Everything seems to be pointing to a higher level of abstraction, but we need to go the other way, as well.
Radojcic: Yes. I know how to simulate temperature in thermal profiles. I can figure out what the thermal profile will look like and I can superimpose it on my die. We can narrow down the problem to a portion of the die. But I don’t know how to import that into timing, because all of our timing is spatially unaware. That, to me, is one of the key EDA disconnects.
Reiter: I see 3D not as a design or implementation methodology, but as a system design methodology. A lot of things we’re seeing on the board level will be reflected in a 3D IC environment.
Gianfagna: Except the proximity effects are significantly worse.
Reiter: Yes, because people who lived on the range before are suddenly moving into a condo building. They cannot behave the same way.

Tags: 2.5D stacking, 3D stacking, Atrenta, BiST, eSilicon, GSA, Hardware Test, Qualcomm

This entry was posted on Friday, January 13th, 2012 at 8:43 am and is filed under Round Tables, Technology Features. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.