Experts At The Table: The Future Of Stacked Die
By Ed Sperling
System-Level Design sat down to discuss the future of stacked die with Riko Radojcic, director of engineering at Qualcomm; Prasad Subramaniam, vice president of design technology at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta; and Herb Reiter, 3D/TSV working group chair for the GSA. What follows are excerpts of that conversation.
SLD: There will need to be an infrastructure of models that are power-aware, interconnect aware and system-aware, right?
Gianfagna: I don’t see how you can express the parameters for those models. Are they accurate enough? I would say no. There is no well-defined set of parameters that characterize this with sufficient detail to be meaningful.
Subramaniam: It will be a challenge to have two thermally alike chips stacked one on top of another. What may ultimately happen is that one chip will be thermally dominant and one will not. That would be an easier problem to address.
Reiter: We have learned a lot in ASICs over the years, and this will be the same. There will be a lot of learning from the data. That’s one of the problems the EDA vendors have now. They can’t get meaningful data from the suppliers. That’s also why they’re reluctant to do a lot of tools right now. If you don’t have good input, the tools without the data will not produce accurate results.
Gianfagna: We know what high-temperature accelerated life testing is for a chip. But what will that be for a 3D stack?
Radojcic: We’ve been pushing this issue of stress awareness for awhile with Sematech, Fraunhofer and Imec. We had a series of workshops to focus on this. The first three were focused on how do we simulate what is basically the DFM. What are the model characteristics you need? The next two were focused on the reliability issues. What are the qualification standards that are required for a 3D stack? Do we need to do something new, or is a 1,000-hour stress test the same?
Gianfagna: I doubt it’s the same. The failure mechanisms are far more varied and subtle.
Radojcic: We’ve already looked at what are the failure mechanisms we should all worry about. There is no doubt stress and the many faces of stress come up on the list. There is a list knocking around of things to worry about. And now we’re going to look at standards.
SLD: Does 3D stacking become harder with 3D structures, such as FinFETs or a deeper channel?
Radojcic: The value proposition for stacking is the same. There is no reason that will go away.
Subramaniam: Those are lower layers. A finFET chip doesn’t look any different than a standard transistor chip.
Radojcic: The reality is no one knows the answer to that. We don’t know if a finFET reacts with a TSV.
Reiter: What happens when we get a much higher software content in 3D? How do we test hardware and software interactions? Software many times causes a lot of headaches. How do we make sure 3D stacking doesn’t get a black eye because the software isn’t mature enough?
Gianfagna: We see the problem very clearly in 2D. My view is 3D won’t be built and thrown over the wall to the software guys. The software guys will be collaborating with the 3D stack design team to build a system. That means the model the software guys are using will not be static and there will have to be an iterative back-and-forth communication with the hardware guys. If software guys are really as invested as the hardware guys, things should be better. It’s not rocket science to solve that problem, but design teams will have to react differently. In my experience, those are the harder problems to solve. To make an organization work differently is much harder than writing a new piece of software.
SLD: How does the business world look at 3D chips? Will it be one vendor producing all of these, or will it multiple of vendors providing lots of different pieces?
Radojcic: Somebody has to be the aggregator. Whether that’s Qualcomm or a third party or the foundry doesn’t matter. But clearly part of the value proposition is intimate interaction with different types of chips, and very few entities design all kinds of chips.
SLD: And the biggest piece of the pie is for the aggregator, right?
Radojcic: Yes. There is money and IP in that space.
Gianfagna: This is like the fabless versus the foundry model. Qualcomm does a lot, but it doesn’t build substrates. Smaller companies will outsource more.
SLD: But your risk goes up with any partnership, right?
Subramaniam: The issue is ownership. Who owns the final product? That will be the aggregator because the aggregator is responsible for putting it all together and making it available to the end customer. In this case, it could be Qualcomm. Or it could be a third party providing it to their own customer.
Radojcic: It also could be an end user like Nokia. That still has to be worked out. It probably will be all of those.
Gianfagna: Let’s look at the seamy underbelly here. The end customer will take all the glory and all the kudos, but they’re not taking the yield risk or the inventory risk. Their supply chain is.
Subramaniam: That’s no different than what’s happening today.
Gianfagna: No, it’s not. But it is more complicated.
Subramaniam: Yes, it makes the problem for the aggregator harder.
Gianfagna: Presumably the aggregator can extract more value for all that additional service.
Reiter: Some companies have already said they will not be the aggregators taking on a lot of responsibility and risk for current margins. The assembly guys already are seeing a big opportunity in this area to become consolidators.
Gianfagna: There are opportunities here for clear thinkers and a little bit of nerve.
Reiter: The problem is some of these guys have just invested millions of dollars in things like wire bonders for SiP, and SiP will largely be replaced.
Radojcic: All of this stuff will co-exist. The TSVs will cost more. There is incremental risk. Some vendors will leverage the incremental value to pay for their costs. But not everything will be that way.
Reiter: But if you look at the I/Os you need SiP. You can’t thin the dies too much because you need to PoP onto this bonding. TSVs, where you are taking the old I/O ring away, make that much more cost-effective. And in two or three years, that will be more cost effective than wire bonding for higher volumes that are architected for 3D.
Radojcic: If you replace the wire bonds with TSVs, the math doesn’t work. It’s too expensive. Wire bonding is a perfectly good, cheap technology.
Subramaniam: For the same number of I/Os, the SiP will be cheaper than the TSV solution. But what TSV offers is the chance to blow up your I/Os. You can have many more I/Os in the same footprint. There will be an incremental cost, but the benefit is significant. You have more connectivity and reduced power. Those are the tradeoffs that need to be made. For applications where that is not necessary, they will tend to use SiP. For applications where you want to take advantage of extra connectivity and low power, that will move to TSVs.
Reiter: What’s the highest pin count in SiP that you have seen? About 500?
Subramaniam: Yes, something like that. Power starts to dominate. There are only so many signals you can put in. You need to have power and ground.
Reiter: From a performance standpoint, TSVs will be much better. The inductance of the bonding wire is huge.
SLD: Who gets hurt by 3D stacking?
Reiter: It’s an incremental opportunity.
Subramaniam: It’s a new technology that offers many more alternatives than are available today. I don’t believe it’s taking away from anybody. It’s adding to the whole space.
Gianfagna: The aggregators will take on more risk with an increased opportunity for reward. The only people who get hurt are the ones who can’t figure out how to use this stuff.
Reiter: Every logic foundry today is a big memory supplier. If memories get pulled out, the logic die gets much smaller and the revenue will get impacted.
Subramaniam: No one will replace SRAM with DRAM. The SRAM will still be there, whether it’s on the same die or different die. You don’t need a different process. I’m not convinced the logic foundries will suffer.
Reiter: But large SRAMs are getting slower than DRAMs because of the wire delay. Having large embedded SRAMs on the SoC is slower than having a DRAM with TSVs on top of it.
Subramaniam: But you can have SRAMs with TSVs through them, as well. And SRAMs are inherently better than DRAMs for that kind of application.
Radojcic: In addition, that’s why you typically partition your SRAM into a whole bunch of smaller instances so you don’t have wire a mile away.
Reiter: But if you look at the wide I/O standard, you can have a lot of small SRAMs on top of your logic-only die.
Radojcic: You could, and there is talk about re-architecting chips to eliminate L3 cache. But it’s not the same value proposition as what’s being enabled by wide I/O.
SLD: What’s the big advantage of 3D? Is it saving money, or is it performance and power?
Reiter: It’s performance and power.
Gianfagna: Performance and power will lead to saving money, not the other way around.
Subramaniam: There are cases where it saves money. In Xilinx’s case, by breaking up the die into four components they were able to significantly improve yield. There will be many cases where by using smaller pieces of silicon and replicating them, either stacking them horizontally or vertically, you will significantly improve yield and get a cost benefit. It’s all of the above.
Tags: 3D stacking, Atrenta, eSilicon, GSA, Qualcomm