System Bits: April 17
Science Behind Networks on Chips
As chipmakers continue to add cores or processing units to keep increasing computational power, the traditional bus structure is running out of steam. The result is that cores need to communicate the same way computers hooked to the Internet do—by bundling the information they transmit into packets, according to researchers at MIT.
Li-Shiuan Peh, an associate professor of electrical engineering and computer science at MIT, said each core would have its own router, which could send a packet down any of several paths, depending on the condition of the network as a whole. Peh and her colleagues have developed two techniques to address these concerns. One is something they call “virtual bypassing.” On the Internet, when a packet arrives at a router, the router inspects its addressing information before deciding which path to send it down. With virtual bypassing, however, each router sends an advance signal to the next, so that it can preset its switch, speeding the packet on with no additional computation. In her group’s test chips, Peh says, virtual bypassing allowed a very close approach to the maximum data-transmission rates predicted by theoretical analysis.
Learn more at this year’s DAC when Peh and her colleagues present a paper on the subject. The researchers establish theoretical limits on the efficiency of packet-switched on-chip communication networks and present measurements performed on a test chip in which they said came very close to reaching several of those limits.
Using the virtual bypassing technique, each router sends an advance signal to the next, so that it can preset its switch, speeding the packet on with no additional computation. Source: MIT
Improving Reliability with Magnetic Testing
To measure the adhesion strength between thin films of materials used in microelectronic devices, photovoltaic cells and microelectromechanical systems (MEMS), researchers at Georgia Tech have developed a new technique that leverages the force generated by magnetic repulsion, which could help ensure the long-term reliability of electronic devices, and assist designers in improving resistance to thermal and mechanical stresses.
Commenting on the fixtureless and non-contact technique, known as the magnetically actuated peel test (MAPT), Suresh Sitaraman, a professor in the George W. Woodruff School of Mechanical Engineering at the Georgia Institute of Technology said, “As we continue to scale down the transistor sizes in microelectronics, the layers will get thinner and thinner,” he said. “Getting to the nitty-gritty detail of adhesion strength for these layers is where the challenge is. This technique opens up new avenues…This technique would help manufacturers know that their products will meet reliability requirements, and provide designers with the information they need to choose the right materials to meet future design specifications over the lifetimes of devices.”
Sitaraman and doctoral student Gregory Ostrowicki have used their technique to measure the adhesion strength between layers of copper conductor and silicon dioxide insulator. They also plan to use it to study fatigue cycling failure, which occurs over time as the interface between layers is repeatedly placed under stress. The technique may also be used to study adhesion between layers in photovoltaic systems and in MEMS devices, the Georgia Tech researchers said.
–Ann Steffora Mutschler
Tags: Georgia Tech, MIT, multicore