The Week In Review: April 27
By Ed Sperling
Mentor Graphics rolled out the next generation of its Veloce2 emulation platform, adding virtualization capabilities. The key here is that it allows software engineers to use the platform to verify their software from their PCs, rather than having to go into a lab to work on their code. This is a new wrinkle in emulation, which is now being used as much for software verification as for hardware. Appealing to software engineers is a whole different world.
Cadence roared back to life in Q1, with revenue increasing to $316 million compared to $266 million in Q1 of 2011. Net income was $31 million compared with $6 million in the same period last year. On a non-GAAP basis, net income was $47 million compared with $23 million in 2010. The company expects revenue of between $315 million and $325 million this quarter.
Synopsys extended visibility in HAPS debug FPGA prototypes, adding about 100 times more storage capacity for signal traces while slashing memory utilization for complex designs.
Open-Silicon expanded its solutions portfolio to include architectural analysis and modeling, pre-silicon prototyping, embedded software, co-silicon system design and test and post-silicon validation. It also expanded its ARM Center of Excellence and boosted staffing at its design center in Pune, India.
Tensilica added support for China’s Dynamic Resolution Adaptation standard to its audio encoder/decoder library for its HiFi Audio DSPs. That should open up a huge market.
Soitec said it is ready to provide fully depleted silicon-on-insulator wafers for both 2D and 3D customers. The company claims significant cost savings over bulk CMOS at advanced nodes—a major shift from previous nodes.
Tags: Cadence, Mentor Graphics, Open-Silicon, Synopsys, Tensilica