The Week In Review: May 4
By Ed Sperling
Apache Design uncorked the next release of its RedHawk power signoff environment, this one geared for sub-20nm and stacked die for designs with more than 3GHz performance and billions of gates. The fact that tools are starting to roll out for 3D ICs is key for moving this design, packaging and re-use scheme forward.
Cadence introduced TripleCheck IP Validator, the latest addition to its verification IP catalog for compliance testing of interface IP. The company also announced availability of its OrCAD Capture Marketplace for its OrCAD and Allegro PCB community through a desktop browser.
Samsung rolled the industry’s first hardened ARM Cortex A-15 SoC utilizing Synopsys’ IC compiler for place and route of the 32nm chip. The chip is based on Samsung’s LP process using high-k/metal gate technology. ARM’s A-15 is its most power processor core yet, and one that it has positioned squarely against Intel.
