The Week In Review: May 18
By Ed Sperling
Cadence added in-circuit acceleration for the Incisive verification and Palladium emulation portions of its System Development Suite. This will reduce the time it takes to run tests on complex SoCs—for both hardware and software—allowing more time to make sure the chip actually works. Cadence also extended its Verification IP catalog for acceleration and emulation. The company also introduced an NVM Express subsystem with pre-integrated and tested IP.
Mentor Graphics won two deals. The first was from U.K.-based Professional Circuit Design, which standardized on Mentor’s PCB design through manufacturing technologies and consulting services.  The second involved Vestel Electronics, a set-top box manufacturer in Europe, which is using Mentor’s Inflexion user interface technology.
Synopsys won a deal with AMD, which will use Synopsys’ Discovery VIP involving everything from USB 3.0, ARM’s AXI, SATA 3.0, PCI Express 3 and Synopsys’ Protocol Analyzer. What makes this especially interesting is AMD’s play in the enterprise space.
MIPS rolled out a new generation of processor cores called Aptiv, with an emphasis on performance and energy efficiency. The cores are targeted at high-end mobile devices and smart home entertainment, squaring off against ARM’s big.LITTLE with what it claims is a much simpler power management scheme.
Tags: AMD, ARM, Cadence, Mentor Graphics, MIPS, Professional Circuit Design, Synopsys, Vestel Electronics