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New Kinds Of Hybrid Chips

By John Blyler and Staff
Crack open any SoC today and it will contain a variety of third-party memory, processor cores, internally and externally developed software and analog. In fact, the main challenge of most chip designs today is integration and software development rather than developing the chip from scratch.

By that definition, almost any chip is a hybrid. But the definition is about to expand significantly over the next few years, as Moore’s Law becomes increasingly difficult to follow and more of the chip is developed in discrete pieces that may go together horizontally, vertically, and sometimes even virtually.

Stacking of die, notably 2.5D configurations, is merely the first step in this process. Going vertical with 2.5D and full 3D versions will likely create a market for subsystems that are silicon-hardened. This makes good sense from a business standpoint, because not every part of the chip needs to be manufactured using the latest process node. In fact, analog developed and verified at older process nodes will likely work fine with a processor core developed at 20nm.

“In general, the trends are toward it being harder and harder from a process technology standpoint for foundries to create a process that is good,” said Hans Bouwmeester, director of IP at Open-Silicon. “That’s true for digital CMOS, for analog, for embedded DRAM and for embedded flash. We’re going to see a lot more heterogeneous die in a package, each in its own process technology. So you’ll have the CPU die in digital using a low-power/high-performance process, a high-speed I/O die with high-speed SerDes, and then you’ll have specialized RF, DRAM, and flash.”

FPGAs could well become part of the stack, as well. In fact, both Xilinx and Altera have created 2.5D planar chips and have commented publicly that they can be used in stacked configurations with other die.

“What you’ll see is that one side will become more specialized,” said Bouwmeester. “The other side will be everything in a package, which opens up enormous possibilities.”

At least part of this is being made possible by software. Getting to tape-out is still a big problem, but it’s certainly not the only one—and maybe not even the biggest. Software development has become a huge challenge. Recent IBS data (see Figure 3) agrees with other evidence that software has become the big driver of cost and schedule. What is unique to the IBS data is confirmation that this trend accelerates at each lower geometric silicon node. Like chip hardware, software—including firmware, operating systems, middleware and even applications—becomes more complex with each generation of Moore’s Law.

Software tends to be the main product differentiator, in large part because hardware has become a commodity—a trend that will likely continue as subsystems and processor platforms become too expensive for most companies to develop. In a “fast market” such as mobile handsets, manufacturers that miss the market by as little as 9 to 12 months may lose $50M to $100M in potential revenue. This revenue loss combined with the extra development time required by software is one reason why software and hardware co-design approaches are so important. In addition, it explains the rise in popularity of virtual and FPGA-based prototype systems and emulation platforms.

Chips also can be built with the assumption that they’re part of a broader communication and storage scheme. Apple’s iCloud is one example of this, where at least some of the processing is done externally, allowing devices to behave almost like thin clients at times, and as fully functional processors at others. This virtualization allows a whole new set of tradeoffs in design, putting as much or more emphasis on the I/O as on the processor and memory.

Mixing and matching
All of these considerations are the result of a big speed bump in IC design, which has forced the semiconductor industry to look elsewhere for gains in performance and efficiency. Double patterning at 20nm has greatly increased the cost of manufacturing, and it will increase further still at 14nm if EUV isn’t commercially viable. They key sticking point there is how many wafers can be processed per hour using EUV. It currently is way too slow to be a viable replacement for 193nm immersion lithography.

But there also is a possibility of double patterning only part of a chip, and developing the rest on the same planar die in an older node. Luigi Capodieci, R&D fellow at GlobalFoundries, noted this is a very real possibility for reducing development costs in the future. But so are new techniques such as directed self-assembly, which can supplement multi-patterning and potentially help keep the cost down.

Still, cost isn’t the only issue that has to be considered. Heat is difficult to remove from chips that are packaged together. While some of that can be programmed away, running a processor at maximum speed for a short period of time and then shutting down, some of it also has to be engineered out with new structures such as FinFETs and new materials such as silicon on insulator (SOI), which can reduce current leakage that causes heat in the first place. What’s new here is that chips may be a combination of all of these things, with companies investing more money in certain portions of a chip—or a die within a package—and reducing costs in other areas. So areas that don’t generate much heat, or functions that aren’t used as often, won’t require as much engineering or the latest process technology and presumably can be done using single patterning.

IC design and manufacturing have been largely evolutionary. After decades of slicing costs at every new process node, it’s difficult to give up on a model that has worked well. The move to 450mm wafers will help boost efficiency even further, providing that yields are reasonable.

However, there is also a growing recognition that not all parts of a chip will continue down the Moore’s Law path at 20nm and beyond. Some portions of an SoC will remain on that path, others will not. But they may all be part of the same aggregate solution, packaged together in unique ways that can actually improve performance, lower power consumption, and get to market on time and with minimal risk of failure.

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